Avalon® Interface Specifications

ID 683091
Date 9/26/2022
Document Table of Contents Pipelined Read Transfers with Fixed Latency

The address phase for fixed latency read transfers is identical to the variable latency case. After the address phase, a pipelined read transfer with fixed read latency takes a fixed number of clock cycles to return valid readdata. The readLatency property specifies the number of clock cycles to return valid readdata. The interconnect captures readdata on the appropriate rising clock edge, ending the data phase.

During the address phase, the agent can assert waitrequest to hold off the transfer. Or, the agent specifies the readLatency for a fixed number of wait states. The address phase ends on the next rising edge of clk after wait states, if any.

During the data phase, the agent drives readdata after a fixed latency. For a read latency of <n>, the agent must present valid readdata on the <nth> rising edge of clk after the end of the address phase.

Figure 13. Pipelined Read Transfer with Fixed Latency of Two CyclesThe following figure shows multiple data transfers between a host and a pipelined agent. The agent drives waitrequest to stall transfers and has a fixed read latency of 2 cycles.

The numbers in this timing diagram, mark the following transitions:

  1. A host initiates a read transfer by asserting read and addr1.
  2. The agent asserts waitrequest to hold off the transfer for one cycle.
  3. The agent captures addr1 at the rising edge of clk. The address phase ends here.
  4. The agent presents valid readdata after 2 cycles, ending the transfer.
  5. addr2 and read are asserted for a new read transfer.
  6. The host initiates a third read transfer during the next cycle, before the data from the prior transfer is returned.