18.104.22.168. Pipelined Read Transfers with Fixed Latency
The address phase for fixed latency read transfers is identical to the variable latency case. After the address phase, a pipelined with fixed read latency takes a fixed number of clock cycles to return valid readdata. The readLatency property specifies the number of clock cycles to return valid readdata. The interconnect captures readdata on the appropriate rising clock edge, ending the data phase.
During the address phase, the can assert waitrequest to hold off the transfer. Or, the specifies the readLatency for a fixed number of wait states. The address phase ends on the next rising edge of clk after wait states, if any.
During the data phase, the drives readdata after a fixed latency. For a read latency of <n>, the must present valid readdata on the <nth> rising edge of clk after the end of the address phase.
The numbers in this timing diagram, mark the following transitions:
- A host initiates a read transfer by asserting read and addr1.
- The asserts waitrequest to hold off the transfer for one cycle.
- The captures addr1 at the rising edge of clk. The address phase ends here.
- The presents valid readdata after 2 cycles, ending the transfer.
- addr2 and read are asserted for a new read transfer.
- The host initiates a third read transfer during the next cycle, before the data from the prior transfer is returned.
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