Avalon® Interface Specifications

ID 683091
Date 9/26/2022
Document Table of Contents

3.5.3. Read and Write Transfers with Fixed Wait-States

A agent can specify fixed wait-states using the readWaitTime and writeWaitTime properties. Using fixed wait-states is an alternative to using waitrequest to stall a transfer. The address and control signals (byteenable, read, and write) are held constant for the duration of the transfer. Setting readWaitTime or writeWaitTime to <n> is equivalent to asserting waitrequest for <n> cycles per transfer.

In the following figure, the agent has a writeWaitTime = 2 and readWaitTime = 1.

Figure 11. Read and Write Transfer with Fixed Wait-States at the Agent Interface

The numbers in this timing diagram mark the following transitions:

  1. The host asserts address and read on the rising edge of clk.
  2. The next rising edge of clk marks the end of the first and only wait-state cycle. The readWaitTime is 1.
  3. The agent asserts readdata and response on the rising edge of clk. The read transfer ends.
  4. writedata, address, byteenable, and write signals are available to the agent.
  5. The write transfer ends after 2 wait-state cycles.

Transfers with a single wait-state are commonly used for multicycle off-chip peripherals. The peripheral captures address and control signals on the rising edge of clk. The peripheral has one full cycle to return data.

Components with zero wait-states are allowed. However, components with zero wait-states may decrease the achievable frequency. Zero wait-states require the component to generate the response in the same cycle that the request was presented.

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