1. Introduction to the Avalon® Interface Specifications 2. Avalon® Clock and Reset Interfaces 3. Avalon® Memory-Mapped Interfaces 4. Avalon® Interrupt Interfaces 5. Avalon® Streaming Interfaces 6. Avalon® Streaming Credit Interfaces 7. Avalon® Conduit Interfaces 8. Avalon® Tristate Conduit Interface A. Deprecated Signals B. Document Revision History for the Avalon® Interface Specifications
2.1. Avalon® Clock Sink Signal Roles 2.2. Clock Sink Properties 2.3. Associated Clock Interfaces 2.4. Avalon® Clock Source Signal Roles 2.5. Clock Source Properties 2.6. Reset Sink 2.7. Reset Sink Interface Properties 2.8. Associated Reset Interfaces 2.9. Reset Source 2.10. Reset Source Interface Properties
5.1. Terms and Concepts 5.2. Avalon® Streaming Interface Signal Roles 5.3. Signal Sequencing and Timing 5.4. Avalon® -ST Interface Properties 5.5. Typical Data Transfers 5.6. Signal Details 5.7. Data Layout 5.8. Data Transfer without Backpressure 5.9. Data Transfer with Backpressure 5.10. Packet Data Transfers 5.11. Signal Details 5.12. Protocol Details
8. Avalon® Tristate Conduit Interface
The Avalon® Tristate Conduit Interface ( Avalon® -TC) is a point-to-point interface designed for on-chip controllers that drive off-chip components. This interface allows data, address, and control pins to be shared across multiple tristate devices. Sharing conserves pins in systems that have multiple external memory devices.
The Avalon® -TC interface restricts the more general Avalon® Conduit Interface in two ways:
- The Avalon® -TC requires request and grant signals. These signals enable bus arbitration when multiple Tristate Conduit Hosts are requesting access to a shared bus.
- The pin type of a signal must be specified using suffixes appended to a signal’s role. The three suffixes are: _out, _in, and _outen. Matching role prefixes identify signals that share the same I/O Pin. The following illustrates the naming conventions for Avalon® -TC shared pins.
Figure 37. Shared Pin Types
The next figure illustrates pin sharing using Avalon® -TC interfaces. This figure illustrates the following points.
- The Tristate Conduit Pin Sharer includes separate Tristate Conduit Agent Interfaces for each Tristate Conduit Host. Each host and agent pair has its own request and grant signals.
- The Tristate Conduit Pin Sharer identifies signals with identical roles as tristate signals that share the same FPGA pin. In this example, the following signals are shared: addr_out, data_out, data_in, read_out, and write_out.
- The Tristate Conduit Pin Sharer drives a single bus including all the shared signals to the Tristate Conduit Bridge. If the widths of shared signals differ, the Tristate Conduit Pin Sharer aligns them on their 0th bit. Tristate Conduit Pin Sharer drives the higher-order pins to 0 whenever the smaller signal has control of the bus.
- Signals that are not shared propagate directly through the Tristate Conduit Pin Sharer. In this example, the following signals are not shared: chipselect0_out, irq0_out, chipselect1_out, and irq1_out.
- All Avalon® -TC interfaces connected to the same Tristate Conduit Pin Sharer must be in the same clock domain.
Figure 38. Tristate Conduit InterfacesThe following illustrates the typical use of Avalon® -TC Host and Agent interfaces and signal naming.