1. Introduction to the Avalon® Interface Specifications
2. Avalon® Clock and Reset Interfaces
3. Avalon® Memory-Mapped Interfaces
4. Avalon® Interrupt Interfaces
5. Avalon® Streaming Interfaces
6. Avalon® Streaming Credit Interfaces
7. Avalon® Conduit Interfaces
8. Avalon® Tristate Conduit Interface
A. Deprecated Signals
B. Document Revision History for the Avalon® Interface Specifications
2.1. Avalon® Clock Sink Signal Roles
2.2. Clock Sink Properties
2.3. Associated Clock Interfaces
2.4. Avalon® Clock Source Signal Roles
2.5. Clock Source Properties
2.6. Reset Sink
2.7. Reset Sink Interface Properties
2.8. Associated Reset Interfaces
2.9. Reset Source
2.10. Reset Source Interface Properties
5.1. Terms and Concepts
5.2. Avalon® Streaming Interface Signal Roles
5.3. Signal Sequencing and Timing
5.4. Avalon® -ST Interface Properties
5.5. Typical Data Transfers
5.6. Signal Details
5.7. Data Layout
5.8. Data Transfer without Backpressure
5.9. Data Transfer with Backpressure
5.10. Packet Data Transfers
5.11. Signal Details
5.12. Protocol Details
8.1. Avalon® Tristate Conduit Signal Roles
The following table lists the signal defined for the Avalon® Tristate Conduit interface. All Avalon® -TC signals apply to both hosts and agents and have the same meaning for both.
Signal Role | Width | Direction | Required | Description |
---|---|---|---|---|
request | 1 | Host → Agent | Yes | The meaning of request depends on the state of the grant signal, as the following rules dictate. When request is asserted and grant is deasserted, request is requesting access for the current cycle. When request is asserted and grant is asserted, request is requesting access for the next cycle. Consequently, request should be deasserted on the final cycle of an access. The request signal deasserts in the last cycle of a bus access. The request signal can reassert immediately following the final cycle of a transfer. This protocol makes both rearbitration and continuous bus access possible if no other hosts are requesting access. Once asserted, request must remain asserted until granted. Consequently, the shortest bus access is 2 cycles. Refer to Tristate Conduit Arbitration Timing for an example of arbitration timing. |
grant | 1 | Agent → Host | Yes | When asserted, indicates that a tristate conduit host has access to perform transactions. The grant signal asserts in response to the request signal. The grant signal remains asserted until 1 cycle following the deassertion of request. |
<name>_in | 1 – 1024 | Agent → Host | No | The input signal of a logical tristate signal. |
<name>_out | 1 – 1024 | Host → Agent | No | The output signal of a logical tristate signal. |
<name>_outen | 1 | Host → Agent | No | The output enable for a logical tristate signal. |