1. Introduction to the Avalon® Interface Specifications 2. Avalon® Clock and Reset Interfaces 3. Avalon® Memory-Mapped Interfaces 4. Avalon® Interrupt Interfaces 5. Avalon® Streaming Interfaces 6. Avalon® Streaming Credit Interfaces 7. Avalon® Conduit Interfaces 8. Avalon® Tristate Conduit Interface A. Deprecated Signals B. Document Revision History for the Avalon® Interface Specifications
2.1. Avalon® Clock Sink Signal Roles 2.2. Clock Sink Properties 2.3. Associated Clock Interfaces 2.4. Avalon® Clock Source Signal Roles 2.5. Clock Source Properties 2.6. Reset Sink 2.7. Reset Sink Interface Properties 2.8. Associated Reset Interfaces 2.9. Reset Source 2.10. Reset Source Interface Properties
5.1. Terms and Concepts 5.2. Avalon® Streaming Interface Signal Roles 5.3. Signal Sequencing and Timing 5.4. Avalon® -ST Interface Properties 5.5. Typical Data Transfers 5.6. Signal Details 5.7. Data Layout 5.8. Data Transfer without Backpressure 5.9. Data Transfer with Backpressure 5.10. Packet Data Transfers 5.11. Signal Details 5.12. Protocol Details
220.127.116.11. Avalon® -MM Read and Write Responses Timing Diagram
The following diagram shows command acceptance and command issue order for Avalon® -MM read and write responses. Because the read and write interfaces share the response signal, an interface cannot issue or accept a write response and a read response in the same clock cycle.
Read responses, send one response for each readdata. A read burst length of <N> results in <N> responses.
Write responses, send one response for each write command. A write burst results in only one response. The agent interface sends the response after accepting the final write transfer in the burst. When an interface includes the writeresponsevalid signal, all write commands must complete with write responses.
Figure 16. Avalon® -MM Read and Write Responses Timing Diagram
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