2022.09.26 |
22.3 |
Added some clarification to the definition of the waitrequestAllowance property in the Interface Properties section. |
2022.01.24 |
20.1 |
Changed the maximum value of the data signal, the dataBitsPerSymbol parameter, and the symbolsPerBeat parameter to 8192 in the Avalon® Streaming Credit Interface Signal Roles section. |
2021.05.27 |
20.1 |
Converted non-inclusive terms to "host" and "agent" inclusive terms for Avalon® interface descriptions throughout the document. |
2021.04.26 |
20.1 |
Added more clarification for the readyLatency property to the Avalon® -ST Interface Properties section. Also added a Note with a description of the Avalon® streaming interconnect that connects Avalon® streaming source/sink BFMs or custom components to the same section. |
2020.12.21 |
20.1 |
Changed references to readyLatency to the correct parameter readLatency in the Pipelined Read Transfers with Fixed Latency section. |
2020.05.26 |
20.1 |
Added more description for the timings diagram Figure 27 in section Data Transfers Using readyLatency and readyAllowance . |
2020.05.07 |
20.1 |
Added some clarification for the timing behavior of the signal writeresponsevalid to the Avalon® Memory-Mapped Interface Signal Roles section. Updated the bus widths for the data and empty signals in the Avalon® Streaming Interface Signal Roles section. |
2020.04.13 |
20.1 |
Added the chapter Avalon® Streaming Credit Interfaces. |
2020.01.03 |
18.1 |
Corrected the definition of the burstOnBurstBoundaries interface property. When true, the burst must begin on a multiple of the maximum burst size. |
2019.10.08 |
18.1 |
Removed references to symbolsPerBeat because it is a deprecated parameter. Added a note in the Data Layout topic to clarify that the Avalon Streaming Interface supports both big-endian and little-endian modes. |
2019.10.03 |
18.1 |
Corrected the property that specifies the fixed latency in the Pipelined Read Transfers with Fixed Latency topic. The readyLatency property, not the readWaitTime property specifies this value. |
2018.09.26 |
18.1 |
In the Write Bursts section, added a statement saying that writes with byteenables being all 0's are passed on to the Avalon® -MM agent as valid transactions. |
2018.09.24 |
18.1 |
In Avalon Memory-Mapped Interface Signal Roles, added consecutive byte-enable support. |
2018.05.22 |
18.0 |
Made the following changes:
- In the Avalon-ST Interface Properties table, corrected the default value for beatsPerCycle. The default value is 1.
- In the Avalon-ST Interface Properties table, added legal values for beatsPerCycle. Legal values are 1, 2, 4, and 8.
- Corrected minor errors and typos.
|
2018.05.07 |
18.0 |
Made the following changes:
- Added support for the readyAllowance parameter.
- Updated the Data Transfers with Backpressure topic to incorporate support for the readyAllowance parameter.
- Fixed minor errors and typos.
|
2018.03.22 |
17.1 |
Made the following changes:
- Made the following changes to the Read and Write Transfers with Waitrequest timing diagram
- Removed readdatavalid signal which is not relevant when using waitrequest
- Moved the number 4, readdata and response forward one cycle.
- Aligned the read signal to number 1.
- Expanded the Transfers Using the waitrequestAllowance Property section. Provided more complex timing diagrams.
- Updated the discussion in the Read Bursts section. For reads with a burstcount > 1, Intel recommends asserting all byteenables.
- Enhanced discussion in the waitrequestAllowance Equals Two - Not Recommended topic. Corrected timing diagram. Data must be held for 2 cycles starting at clock cycle 11.
|
November 2017 |
17.1 |
Made the following changes:
- Updated the discussion of Read Bursts as follows:
- Qualified the statement, " When a host connects directly to a agent, a burstcount of <n>, means the agent must return <n> words of readdata to complete the burst. " This statement is true if the host connects directly to the agent. It may not be true if interconnect links the host and agent.
- Removed the following statement from the description of read bursts: "The byteenables presented with a read burst command apply to all cycles of the burst." This statement is no longer true. However, Intel recommends that reads with burstcount > 1 assert all byteenables.
- Removed the following statement form the Pipelined Transfers section: Write transfers cannot be pipelined. You can pipeline writes using the writeresponsevalid signal.
- Expanded the description of read and write responses in the Avalon® -MM Read and Write Responses Timing Diagram section.
- Revised the description of the reset_req signal.
- Changed width of irq from 1 bit to 1-32 bits. Both the Intel® Quartus® Prime Pro Edition and Intel® Quartus® Prime Standard Edition software support interrupt vectors.
|
May 2017 |
Quartus® Prime Pro v17.1 Stratix® 10 ES Editions |
Made the following changes:
- Added the following interface property parameters.
- waitrequestAllowance parameter to support high speed operation. This parameter is available for Avalon-MM interfaces. Added timing diagrams illustrating use of this parameter.
- minimumResponseLatency parameter to facilitate timing closure for Avalon-MM interface. Added timing diagrams illustrating use of this parameter.
|
December 2015 |
15.1 |
Made the following changes:
- Changed the width of the empty signal from a maximum of 8 bits to a maximum of 5 bits.
- Improved the definition of the reset_req signal.
- Removed the readdatavalid signal from the Pipelined Read Transfer with Fixed Latency of Two Cycles timing diagram. This signal is not relevant for fixed latency transfers.
- Corrected equation defining the empty signal.
- Made the following changes in the Pipelined Read Transfers with Variable Latency timing diagram:
- Moved the deassertion of the read signal to cycle 9
- Changed waitrequest to don't care in cycle 9.
|
March 2015 |
14.1 |
Fixed typo in Figure 1-1. |
January 2015 |
14.1 |
Made the following changes:
- Clarified address alignment example. The Avalon-MM host and agent interfaces are different widths.
- Improved discussion of Pipelined read Transfers with Variable Latency. Corrected timing marker 2 which should be exactly on the rising edge of clock.
- Improved discussion of Pipelined Read Transfer with Fixed Latency of Two Cycles.
- Clarified use of beatsPerCycle property.
- Corrected the address range for line-wrapped bursts. The correct address range for a 64-byte burst is 0x0–0x3C, not 0x0–0x1C.
- Corrected description of the Tristate Conduit Arbitration Timing diagram in the following ways:
- The tristate conduit agent asserts grant, not the tristate conduit host.
- The final grant comes in cycle 9, not cycle 8.
- Added a Deprecated Signals appendix.
- Added read response signal.
- Improved definitions of clock and reset signal types.
- Corrected definition of clock sink properties.
- Corrected definition of synchronousEdges for reset source interface.
- Clarified the Avalon-MM response signal type.
- Updated definition of empty. The signal must be interpreted emptyWithinPacket is true.
- Edited for clarity and consistency.
|
June 2014 |
14.0 |
- Updated the Avalon-MM Signals table, begintransfer, readdatavalid, and readdatavalid_n.
- Updated the Read and Write Transfers with Waitrequest figure:
- Moved deassertion of write to cycle 6.
- Moved assertion of readdatavalid and readdata to cycle 4.
- Updated the Pipelined Read Transfers with Variable Latency figure:
- Moved assertion of data1 to just after cycle 5, and assertion of data2 to cycle 6.
- Moved assertion of readdatavalid to match data1 and data2.
|
April 2014 |
13.01 |
Corrected Read and Write Transfers with Waitrequest In Avalon Memory-Mapped Interfaces chapter . |
May 2013 |
13.0 |
Made the following changes:
- Minor updates to Avalon Memory-Mapped Interfaces.
- Minor updates to Avalon Streaming Interfaces.
- Updated Avalon Conduit Interfaces to describe the signal roles supported by Avalon conduit interfaces.
- Updated Shared Pin Types figure in the Avalon Tristate Conduit Interface chapter.
|
May 2011 |
11.0 |
Initial release of the Avalon Interface Specifications. |
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