1. Introduction to the Avalon® Interface Specifications 2. Avalon® Clock and Reset Interfaces 3. Avalon® Memory-Mapped Interfaces 4. Avalon® Interrupt Interfaces 5. Avalon® Streaming Interfaces 6. Avalon® Streaming Credit Interfaces 7. Avalon® Conduit Interfaces 8. Avalon® Tristate Conduit Interface A. Deprecated Signals B. Document Revision History for the Avalon® Interface Specifications
2.1. Avalon® Clock Sink Signal Roles 2.2. Clock Sink Properties 2.3. Associated Clock Interfaces 2.4. Avalon® Clock Source Signal Roles 2.5. Clock Source Properties 2.6. Reset Sink 2.7. Reset Sink Interface Properties 2.8. Associated Reset Interfaces 2.9. Reset Source 2.10. Reset Source Interface Properties
5.1. Terms and Concepts 5.2. Avalon® Streaming Interface Signal Roles 5.3. Signal Sequencing and Timing 5.4. Avalon® -ST Interface Properties 5.5. Typical Data Transfers 5.6. Signal Details 5.7. Data Layout 5.8. Data Transfer without Backpressure 5.9. Data Transfer with Backpressure 5.10. Packet Data Transfers 5.11. Signal Details 5.12. Protocol Details
5.9.2. Data Transfers Using readyLatency
If the source or the sink do not specify a value for readyAllowance then readyAllowance= readyLatency. Designs that use source and sink do not require the addition of readyAllowance unless you want the source or the sink to take advantage of this feature.
Figure 28. Transfer with Backpressure, readyLatency=0The following figure illustrates these events:
- The source provides data and asserts valid on cycle 1, even though the sink is not ready.
- The source waits until cycle 2, when the sink does assert ready, before moving onto the next data cycle.
- In cycle 3, the source drives data on the same cycle and the sink is ready to receive data. The transfer occurs immediately.
- In cycle 4, the sink asserts ready, but the source does not drive valid data.
Figure 29. Transfer with Backpressure, readyLatency=1The following figures show data transfers with readyLatency=1 and readyLatency=2, respectively. In both these cases, ready is asserted before the ready cycle, and the source responds 1 or 2 cycles later by providing data and asserting valid. When readyLatency is not 0, the source must deassert valid on non-ready cycles.
Figure 30. Transfer with Backpressure, readyLatency=2
Did you find the information on this page useful?