F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 1/07/2022

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Document Table of Contents

4.2.1. MAC TX Datapath

The below sections are applicable for both, TX MAC Avalon ST interface and TX MAC segmented interface.

When the TX MAC module in a channel is enabled, it receives the client payload data with the destination and source addresses and then adds, appends, or updates various header fields in accordance with the configuration specified. The MAC does not modify the destination address or the payload received from the client. However, the TX MAC module adds a preamble (if the IP core is not configured to receive the preamble from user logic), pads the payload of frames greater than eight bytes to satisfy the minimum Ethernet frame payload of 46 bytes, and if you enable source address insertion, replaces the bytes in the source address field position of your data with a stored source address you provide as a parameter.


The TX MAC interface does not support non-contiguous transfer. The i_tx_valid or i_tx_mac_valid must be continuously asserted between the assertions of the start of packet and end of packet signals for the same packet. You must implement store and forward packet mechanism when transferring non-contiguous packets.

When TX MAC interface ready signal indicates low, if you use MAC Avalon ST interface, the valid signal may go low. If you use MAC segmented interface, the valid signal must go low.

The client interface includes a port named i_tx_skip_crc or i_tx_mac_skip_crc, which when asserted during a frame, makes the MAC skip the insertion of source address, padding, and CRC.

  • When CRC insertion is skipped, the client must provide a CRC for the frame data it writes in the last 4 bytes of the frame.
  • When padding is skipped, the frame data must be large enough to include a fully formed frame header (at least 14 bytes long) or the MAC will automatically mark it as an error frame.

The TX MAC module always inserts IDLE bytes to maintain an average IPG.

The F-Tile Ethernet Intel® FPGA Hard IP drops incoming frames of less than nine bytes.

Figure 5. Typical Client Frame at the Transmit InterfaceThe figure illustrates the changes that the TX MAC makes to the client frame when Enable Preamble Passthrough is turned off. This figure uses the following notational conventions:
  • <p> = payload size, which is arbitrarily large.
  • <s> = number of padding bits (0–46 bytes)
  • <g> = number of IPG bits (full bytes)

The following sections describe the functions performed by the TX MAC: