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7.9. FlexE and OTN Mode TX Interface
The F-Tile Ethernet Intel® FPGA Hard IP TX client interface in FlexE and OTN variations employs the PCS66 interface protocol.
The FlexE and OTN variations allow the application to write 66b blocks to the TX PCS, bypassing the TX MAC.
- In FlexE mode and 200GE/400GE OTN modes, the TX encoder in the PCS is also bypassed.
- In 10GE/25GE/40GE/50GE/100GE OTN mode, both the TX encoder and the scrambler are bypassed.
The client acts as a source and the TX PCS acts as a sink in the transmit direction.
1056 bits (400GE)
528 bits (200GE)
264 bits (100GE)
132 bits (40GE/50GE)
TX PCS 66b data for 1 block.
|1 bit||When asserted, indicates that the TX PCS 66b data is valid.
Must be asserted when the TX PCS 66b ready signal is asserted.
TX PCS 66b ready signal.
When asserted, indicates the PCS is ready to receive new data.
|1 bit for each channel||Alignment marker insertion bit.
In FlexE mode, asserting this signal causes the PCS to allow gaps for the alignment markers in place of the data presented on the TX PCS data signal. The application marks the block as an alignment marker and the scrambler does not process the data.
In OTN mode, RS-FEC must be aware of the alignment marker location.
In OTN mode without FEC, the i_tx_pcs66_am signal is optional. You can tie it low.
TX data is written as 66b blocks. The blocks are expected to be 66b encoded, with the sync header bits in the rightmost bit positions (bits 1 and 0).
- In FlexE mode, the PCS scrambles and stripes the blocks for transmission.
- In OTN mode, the PCS only stripes the blocks for transmission. The input data is expected to be already scrambled.
i_tx_pcs66_valid should conform to these conditions:
- Assert the valid signal only when the ready signal is asserted, and deassert only when the ready signal is deasserted.
- The two signals can be spaced by a fixed latency between 1 and 6 cycles.
- When the valid signal deasserts, i_tx_pcs66_d must be paused.
The block order for the PCS66 mode TX interface is the same as the TX PCS interface. Blocks are transmitted from LSB to MSB; the first block to be transmitted from the interface is i_tx_pcs66_d[65:0].
The bit order for the PCS66 mode TX interface is the same as the TX PCS interface. Bits are transmitted from least to most significant; the first bit to be transmitted from the interface is i_tx_pcs66_d.
When the PCS66 TX interface is used for FlexE mode, the timing of alignment marker insertion can be controlled from the fabric. The same operations can be performed on single lane variants, with slight variance:
- For 40GE/50GE/100GE/200GE/400GE channels and 25GE channel with RS-FEC, the signal causes the alignment markers to be inserted.
- For 10GE/25GE channels with no RS-FEC or Firecode, the signal causes the cycle to be treated as invalid for PCS processing (no changes to scramble).
In FlexE mode, the timing of alignment marker insertion is very rigid. Alignment markers cannot be delayed without disrupting the Ethernet link. Use valid cycles to count the alignment markers. When i_tx_pcs66_valid is low, the alignment marker counters and input must freeze.
OTN streams are expected to include their own alignment markers. In OTN mode with FEC, you must assert i_tx_pcs66_am to indicate the position of the alignment markers. In OTN mode without FEC, i_tx_pcs66_am is optional and you can tie the signal low.
In FEC modes, the TX datapath does not come completely out of reset until at least 2 alignment marker periods passed. You must start driving i_tx_pcs66_am at the proper interval before o_tx_lanes_stable goes high. You may drive the signal as soon as o_tx_pll_locked has gone high and o_tx_pcs66_ready starts toggling. When the external custom rate interface is enabled, you must start driving i_custom_cadence. For more information, refer to the Custom Rate Interface.
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