F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 1/07/2022
Public

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9.1.4. Parameters

The F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP parameter editor provides the parameters you can set to configure your IP variation.

The F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP parameter has an AN/LT Options tab and an AN Channel Map tab.

Table 67.   F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP Parameters: IP TabThis table does not provide information about invalid parameter value combinations. If you make selections that create a conflict, the parameter editor generates error messages in the System Messages pane.

Parameter

Range

Default Setting

Parameter Description

Mode selection
Enable auto-negotiation on reset
  • On
  • Off
On Enable Auto-negotiation.
Enable link training on reset
  • On
  • Off
On Enable Link Training.
Enable ECC protection
  • On
  • Off
Off Enable Error Correction Code (ECC) for Nios® II memory.

To enable this feature, you must acquire Nios® II license. Contact Intel Sales for information about acquiring a license.

PMA type
  • FHT
  • FGT
FGT

PMA Type.

Selects the PMA type. Each PMA has a different data rate range and compliance specifications.

The selected mode must match with PMA mode selected in Base IP.

Ethernet mode
  • 10GE-1
  • 25GE-1
  • 40GE-4
  • 50GE-2
  • 50GE-1
  • 100GE-4
  • 100GE-2
  • 100GE-1
  • 200GE-8
  • 200GE-4
  • 200GE-2
  • 400GE-8
  • 400GE-4
10GE-1

Ethernet Configuration.

Specifies the overall port bandwidth across the number of physical lanes used by the port.

Term XGbE-Y represents:
  • X is the overall bandwidth of the port
  • Y is the number of physical lanes used by port

The selected mode must match with Ethernet mode selected in Base IP.

KR or CR mode
  • KR mode
  • CR mode
CR mode Selects the option during auto-negotiation.
Number of ports 1-16 4 Selects number of base Ethernet IP ports connected to the IP.
FEC mode
  • None
  • IEEE 802.3 BASE-R Firecode (CL74)
  • IEEE 802.3 RS(528,514) (CL91) or

    IEEE 802.3

    RS(544,514)

    (CL134)

  • Ethernet Technology Consortium RS(272, 258)
None

Selects the FEC mode for each port.

The IP core supports the following FEC types
  • IEEE 802.3 BASE-R Firecode (CL74) is available only for 25GE-1.
  • IEEE 802.3 RS(528,514) (CL91)

  • IEEE 802.3 RS(544,514) (CL134)

  • Ethernet Technology Consortium RS(272,258) is a low-latency substitute for RS(544,514).
Link fail inhibit time 0-20000
  • 505 (for NRZ)
  • 3150 (for 50G PAM4)
  • 12350 (for 100G PAM4)

Sets the link fail inhibit timeout for auto-negotiation in milliseconds.

Default value:
  • 505 ms for NRZ modes
  • 3150 ms for 50G PAM4 modes
  • 12350 ms for 100G PAM4 modes
Status clock frequency 100-250 100

Selects the auto-negotiation and link training status clock frequency.

Must be set to the frequency of the i_clk input for the correct timer functionality.

AN Channel Map

AN channel

AN channel location <n>

0-7

0

Selects the AN lane default location in each Ethernet ports. <n> is an integer from 0 to (number of lanes - 1). For example, for 100GE-4, AN channel location <n> parameter can be 0 to 3.

This option is not available for single lane (For example, 10GE-1, 25GE-1).

Note: The VHDL file format is not available for simulation and synthesis in the F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP. When you enable auto-negotiation in your design, you must select the Verilog generated file format in the IP Parameter Editor GUI for both IPs, F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP and F-Tile Ethernet Intel® FPGA Hard IP.