F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 1/07/2022

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5.5. Clock Connections in Synchronous Ethernet Operation

When you enable the Synchronous Ethernet (SyncE) operation, two or more channels can share the off-chip cleanup PLL clock output.

The Synchronous Ethernet standard, described in the ITU-T G.8261, G.8262, and G.8264 recommendations, requires that the TX clock be filtered to maintain synchronization with the RX reference clock through a sequence of nodes. The expected usage is that user logic drives the transceiver reference clocks with a filtered version of the RX recovered clock signal, to ensure the receive and transmit functions remain synchronized. In this usage model, a design component outside the IP core performs the filtering off chip.

The primary SyncE clock and the backup SyncE clock come from the recovered clock output pins of channels connected to the same SyncE network while i_clk_ref clock connects to the cleanup PLL. You can combine SyncE clocking with the data path clocking. The channels don't have to be part of the same IP core instance or same IP core variant.

Figure 22. Clock Connections in SyncE Operation
You can use both o_clk_rec_div and o_clk_rec_div64 output clocks to drive the primary and backup SyncE clocks.
Note: You must set the Custom Cadence mode to match the PPM difference between clocks when the IP core system clock is derived from a different reference clock than the transceiver clock.