F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 1/07/2022

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Document Table of Contents

4.3.3. FlexE Mode

The F-Tile Ethernet Intel® FPGA Hard IP supports all flexible Ethernet mode variants with optional RS-FEC feature. This mode bypassed the Ethernet MAC and uses PCS66 interface to read and write to the PMA block.

The TX FlexE datapath consists of:
  • TX PCS scrambler—enables the data to be scrambled. Channels does not lock correctly if the data is not scrambled.
  • Alignment insertion—the TX PCS interface inserts alignment markers
  • Striper—enables logically sequential data to be segmented to increase data throughput.
The RX FlexE datapath consists of:
  • Aligner—enables the alignment of incoming data.
  • RX PCS descrambler—enables the incoming scrambled data to be descrambled.