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1. Overview 2. Getting Started 3. F-Tile Ethernet Intel® FPGA Hard IP Parameters 4. Functional Description 5. Clocks 6. Resets 7. Interface Overview 8. Configuration Registers 9. Supported Modules and IPs 10. Supported Tools 11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives 12. Document Revision History
4.4.1. Features 4.4.2. PTP Timestamp Accuracy 4.4.3. PTP Client Flow 4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants 4.4.5. Virtual Lane Order and Offset Values 4.4.6. UI Adjustment 4.4.7. Reference Time Interval 4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 4.4.9. UI Value and PMA Delay 4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode
5.1. Clock Connections in Single Instance Operation 5.2. Clock Connections in Multiple Instance Operation 5.3. Clock Connections in MAC Asynchronous FIFO Operation 5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation 5.5. Clock Connections in Synchronous Ethernet Operation 5.6. Custom Cadence
7.1. Status Interface 7.2. TX MAC Avalon ST Client Interface 7.3. RX MAC Avalon ST Aligned Client Interface 7.4. TX MAC Segmented Client Interface 7.5. RX MAC Segmented Client Interface 7.6. MAC Flow Control Interface 7.7. PCS Mode TX Interface 7.8. PCS Mode RX Interface 7.9. FlexE and OTN Mode TX Interface 7.10. FlexE and OTN Mode RX Interface 7.11. Custom Rate Interface 7.12. Reconfiguration Interfaces 7.13. Precision Time Protocol Interface
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough 7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough 7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
5.2. Clock Connections in Multiple Instance Operation
This clock connection describes multiple IP core instantiations in your design.
This is a recommended clocking for multiple IP core clock connections.
You must make the following clock connections:
- The i_clk_ref and the i_clk_sys clocks drives all instantiated IP cores.
- The output clock o_clk_pll of a single IP core can drive all instantiated IP core i_clk_rx and the i_clk_tx input signals under the following conditions:
- The shared clock is traceable to a common source reference clock.
- The F-Tile Ethernet Intel® FPGA Hard IP uses the same rate to configure the its port system clocks.
Figure 19. Clock Connections for Multiple IP Cores
The following are examples of alternative clock sources satisfying the clock connections requirements:
- Another IP instance's o_clk_pll output clock can drive an IP core specific i_clk_rx and the i_clk_tx input signals provided that their respective reference clocks are configured at the same rate.
- An IO PLL can drive an IP core related input clock signals provided that the PLL and IP core derive their i_clk_ref reference clock from the same reference clock source.
- A GPIO, directly connected to the reference clock, with frequency of 161.1328125 MHz, can directly drive the i_clk_rx and the i_clk_tx input signals.
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