F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 1/07/2022

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Document Table of Contents Frame Check Sequence (CRC-32) Insertion

If the i_tx_skip_crc or i_tx_mac_skip_crc signal on the TX client interface is not asserted, the TX MAC computes and inserts a frame check sequence (FCS) in the transmitted MAC frame. The FCS field contains a 32-bit Cyclic Redundancy Check (CRC32) value. The MAC computes the CRC32 over the frame bytes that include the source address, destination address, length/type field, data, and pad (if applicable). The FCS computation excludes the preamble and SFD. The encoding is defined by the following generating polynomial:

FCS(X) = X32 +X26 +X23 +X22 +X16 +X12 +X11 +X10 +X8 +X7 +X5 +X4 +X2 +X1 +1

CRC bits are transmitted with MSB (X32) first.

If i_tx_skip_crc or i_tx_mac_skip_crc is asserted while writing frame data, the TX MAC does not append an FCS to the end of the frame. This causes the resulting packet to be invalid unless the last 4 bytes of frame data are a correctly computed FCS value.

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