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2.5. Generating Tile Files
You can use the Support-Logic Generation command on the Processing menu in the Intel® Quartus® Prime Pro Edition software to generate the F-tile specific tiles your design. Alternatively, you can run quartus_tlg command prompt to generate these files.
Starting with the Intel® Quartus® Prime software version 21.4, the Support-Logic Generation command is run automatically when you generate your design using F-Tile Ethernet Intel® FPGA Hard IP Example Design IP Parameter Editor.
A successful tile file generation results in the eth_f_hw_tiles.x files where x represents necessary file extensions. The generated files are located in your project directory and contain the full netlist for simulation and synthesis.
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