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1. Overview 2. Getting Started 3. F-Tile Ethernet Intel® FPGA Hard IP Parameters 4. Functional Description 5. Clocks 6. Resets 7. Interface Overview 8. Configuration Registers 9. Supported Modules and IPs 10. Supported Tools 11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives 12. Document Revision History
4.4.1. Features 4.4.2. PTP Timestamp Accuracy 4.4.3. PTP Client Flow 4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants 4.4.5. Virtual Lane Order and Offset Values 4.4.6. UI Adjustment 4.4.7. Reference Time Interval 4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 4.4.9. UI Value and PMA Delay 4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode
5.1. Clock Connections in Single Instance Operation 5.2. Clock Connections in Multiple Instance Operation 5.3. Clock Connections in MAC Asynchronous FIFO Operation 5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation 5.5. Clock Connections in Synchronous Ethernet Operation 5.6. Custom Cadence
7.1. Status Interface 7.2. TX MAC Avalon ST Client Interface 7.3. RX MAC Avalon ST Aligned Client Interface 7.4. TX MAC Segmented Client Interface 7.5. RX MAC Segmented Client Interface 7.6. MAC Flow Control Interface 7.7. PCS Mode TX Interface 7.8. PCS Mode RX Interface 7.9. FlexE and OTN Mode TX Interface 7.10. FlexE and OTN Mode RX Interface 7.11. Custom Rate Interface 7.12. Reconfiguration Interfaces 7.13. Precision Time Protocol Interface
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough 7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough 7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
7.1. Status Interface
The F-Tile Ethernet Intel® FPGA Hard IP core provides a handful of status signals to support visibility into the actions of the IP core and the stability of IP core output clocks.
In non-FEC and Firecode FEC variant, asserted when the IP core completes 66-bit block boundary alignment on all PCS lanes.
Otherwise, asserted when the IP core completes the codeword alignment on all FEC lanes.
|o_rx_am_lock||Asserted when the RX PCS completes detection of alignment markers and deskew of the PCS lanes.
Not supported for 10G/25G variants.
|o_local_fault_status||Asserted when the RX MAC detects a local fault: the RX PCS detected a problem that prevents it from receiving data. This signal is functional only if you set the Client Interface parameter to the value of MAC segmented or MAC Avalon ST in the parameter editor.|
|o_remote_fault_status||Asserted when the RX MAC detects a remote fault: the remote link partner sent remote fault ordered sets indicating that it is unable to receive data. This signal is functional only if you set the Client Interface parameter to the value of MAC segmented or MAC Avalon ST in the parameter editor.|
|i_stats_snapshot||Directs the IP core to record a snapshot of the current state of the statistics registers. Assert this signal to perform the function of both the TX and RX statistics register shadow request fields at the same time, or to perform that function for multiple instances of the IP core simultaneously.
This signal is synchronous with the i_clk_tx clock.
|o_rx_hi_ber||Asserted to indicate the RX PCS is in a HI BER state according to Figure 82-15 in the IEEE 802.3-2015 Standard. The IP core uses this signal in auto negotiation and link training.|
|o_rx_pcs_fully_aligned||Asserts when RX PCS is ready to receive data.|
Figure 25. Status Interface Behavior during Link Startup with Bidirectional Link FaultThe waveform displays the status signal behavior in the IP core at the startup.
Figure 26. Status Interface Behavior during Link Startup with Unidirectional or Link Fault DisableThe waveform displays status signals behavior in the IP core at the startup.
Figure 27. Status Interface Behavior during Freezing i_stats_snapshot The waveform displays an event when i_stats_snapshot signal is used to freeze the statistics CSRs. Note that the underlying counters continue to track the IP core events.
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