F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 1/07/2022
Public

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6.1. Reset Signals

The IP core has four soft reset inputs. These resets are asynchronous and are internally synchronized.
Table 29.  Reset SignalsAll specified resets are asynchronous.
Signal Description
Input Signals
i_rst_n

Active-low reset asynchronous signal. Do not deassert until the o_rst_ack_n deasserts.

  • Resets the TX interface, including the TX PCS and TX MAC.
  • Resets the RX interface, including the RX PCS and RX MAC.
  • Resets the TX PMA and TX EMIB.
  • Resets the RX PMA and RX EMIB.

This reset leads to assertion of the o_rst_ack_n output signal.

i_tx_rst_n

Active-low reset asynchronous signal. Resets the entire TX datapath, including the TX PCS, TX MAC, TX PMA, and TX EMIB. Do not deassert until the o_rst_ack_n asserts.

i_rx_rst_n

Active-low reset asynchronous signal. Resets the entire RX datapath, including the RX PCS, RX MAC, RX PMA, and RX EMIB. Do not deassert until the o_rst_ack_n asserts.

i_reconfig_reset

Active-high reconfiguration reset signal. Reset the entire reconfiguration clock domain, including the soft registers (CSRs).

You must assert this reset after power-on or during the configuration. The i_reconfig_clk must be stable before deasserting this reset.

Output Signals
o_rst_ack_n

Active-low asynchronous acknowledgement signal for the i_rst_n reset.

Do not deassert i_rst_n reset until the o_rst_ack_n asserts.

o_tx_rst_ack_n

Active-low asynchronous acknowledgement signal for the i_tx_rst_n reset.

Do not deassert i_tx_rst_n reset until the o_tx_rst_ack_n asserts.

o_rx_rst_ack_n

Active-low asynchronous acknowledgement signal for the i_rx_rst_n reset.

Do not deassert i_rx_rst_n reset until the o_rx_rst_ack_n asserts.

Status Signals
o_tx_lanes_stable Active-high asynchronous status signal for the TX datapath.
  • Asserts when the TX datapath is ready to send data.
  • Deasserts when i_tx_rst_n/i_rst_n signal asserts or during the auto-negotiation and link training operation.
o_rx_pcs_ready Active-high asynchronous status signal for the RX datapath.
  • Asserts when the RX datapath is ready to receive data.
  • Deasserts when i_rx_rst_n/i_rst_n signal asserts or during the auto-negotiation and link training operation.

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