F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 1/07/2022

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Document Table of Contents

9.2.2. Clocks, Reset, and Interface Ports

Table 71.  Clock Ports
Name Description
i_sys_clk Clock source to drive TX deskew pulse generation logic. Must be connected to the F-Tile Reference and System PLL Clock Intel® FPGA IP clock source (o_clk_pll).

The clock frequency is equivalent to a half of a system PLL frequency, specified by the System PLL frequency parameter. The minimal frequency is 402.83 MHz.

i_reconfig_clk Reconfiguration clock for Avalon® memory-mapped interface.

Clock derived from the F-Tile Reference and System PLL Clock Intel® FPGA IP associated with the Ethernet IP port. The o_clk_pll frequency is equal to PLL frequency divided by 2.

When PTP is enabled, the PTP tile adapter's o_clk_pll is a clock input to the i_clk_tx, i_clk_rx Ethernet clocks, and i_clk_pll for Asynchronous mode, for all Ethernet modes.

Table 72.  Reset Ports
Name Description
i_rst_n Active-low reset signal for TX deskew pulse generation logic.

The i_sys_clk must be stable before deasserting this reset.

Intel recommends to connect the reset to the o_tx_pll_locked output clock status signal of an active Ethernet IP port.


Active-high reconfiguration reset signal. Reset the entire reconfiguration clock domain.

You must assert this reset after power-on or during configuration. The i_reconfig_clk must be stable before deasserting this reset.

Table 73.  Interface Ports
Name Description
ptp_link Represents a logical connection between PTP Tile Adapter and the Ethernet IP with enabled PTP.

During Support-Logic Generation, if the ptp_link is connected, the IP flow generates a PTP signal bus between the PTP Tile Adapter and one or more Ethernet IP with enabled PTP option within the same F-tile design.