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Ixiasoft
1.7.11. HPS SPI管脚
注: 英特尔建议您创建一个 英特尔® Quartus® Prime设计,输入您的器件I/O分配并编译设计。 英特尔® Quartus® Prime软件将会根据I/O分配和布局规则对管脚连接进行检查。这些规则因不同器件而异,这取决于器件密度、封装、I/O分配、电压分配以及其他未在本文档或器件手册中充分说明的因素。
HPS管脚功能 | 管脚说明和连接指南 | 管脚类型 | 有效分配(从其中的一组中选择) | ||
---|---|---|---|---|---|
Group 1 | Group 2 | Group 3 | |||
SPIM0_CLK | SPIM0 Clock | 输出 | HPS_IOA_5 | HPS_IOB_21 | HPS_IOB_21 |
SPIM0_MOSI | SPIM0 Master Out Slave In | 输出 | HPS_IOA_6 | HPS_IOB_22 | HPS_IOB_22 |
SPIM0_MISO | SPIM0 Master In Slave Out | 输入 | HPS_IOA_7 | HPS_IOB_19 | HPS_IOB_23 |
SPIM0_SS0_N | SPIM0 Slave Select 0 这是一个低电平有效(active-low)信号。 |
输出 | HPS_IOA_8 | HPS_IOB_20 | HPS_IOB_24 |
SPIM0_SS1_N | SPIM0 Slave Select 1 这是一个低电平有效(active-low)信号。 |
输出 | HPS_IOA_1 | HPS_IOB_18 | HPS_IOB_18 |
SPIM1_CLK | SPIM1 Clock | 输出 | HPS_IOA_9 | HPS_IOA_21 | HPS_IOB_1 |
SPIM1_MOSI | SPIM1 Master Out Slave In | 输出 | HPS_IOA_10 | HPS_IOA_22 | HPS_IOB_2 |
SPIM1_MISO | SPIM1 Master In Slave Out | 输入 | HPS_IOA_11 | HPS_IOA_23 | HPS_IOB_3 |
SPIM1_SS0_N | SPIM1 Slave Select 0 这是一个低电平有效(active-low)信号。 |
输出 | HPS_IOA_12 | HPS_IOA_24 | HPS_IOB_4 |
SPIM1_SS1_N | SPIM1 Slave Select 1 这是一个低电平有效(active-low)信号。 |
输出 | HPS_IOA_2 | HPS_IOA_20 | HPS_IOB_5 |
SPIS0_CLK | SPIS0 Clock | 输入 | HPS_IOA_1 | HPS_IOA_21 | HPS_IOB_9 |
SPIS0_MOSI | SPIS0 Master Out Slave In | 输入 | HPS_IOA_2 | HPS_IOA_22 | HPS_IOB_10 |
SPIS0_MISO | SPIS0 Master In Slave Out | 输出 | HPS_IOA_4 | HPS_IOA_24 | HPS_IOB_12 |
SPIS0_SS0_N | SPIS0 Slave Select 0 这是一个低电平有效(active-low)信号。 |
输入 | HPS_IOA_3 | HPS_IOA_23 | HPS_IOB_11 |
SPIS1_CLK | SPIS1 Clock | 输入 | HPS_IOA_9 | HPS_IOB_5 | HPS_IOB_21 |
SPIS1_MOSI | SPIS1 Master Out Slave In | 输入 | HPS_IOA_10 | HPS_IOB_6 | HPS_IOB_22 |
SPIS1_MISO | SPIS1 Master In Slave Out | 输出 | HPS_IOA_12 | HPS_IOB_8 | HPS_IOB_24 |
SPIS1_SS0_N | SPIS1 Slave Select 0 这是一个低电平有效(active-low)信号。 |
输入 | HPS_IOA_11 | HPS_IOB_7 | HPS_IOB_23 |