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1.7.6. HPS NAND管脚
注: 英特尔建议您创建一个 英特尔® Quartus® Prime设计,输入您的器件I/O分配并编译设计。 英特尔® Quartus® Prime软件将会根据I/O分配和布局规则对管脚连接进行检查。这些规则因不同器件而异,这取决于器件密度、封装、I/O分配、电压分配以及其他未在本文档或器件手册中充分说明的因素。
HPS管脚功能 | 管脚说明和连接指南 | 管脚类型 | 有效分配(从其中的一组中选择) | |
---|---|---|---|---|
Group 1 | Group 2 | |||
NAND_ADQ0 | NAND Data Bit 0 | I/O | HPS_IOA_1 | HPS_IOB_1 |
NAND_ADQ1 | NAND Data Bit 1 | I/O | HPS_IOA_2 | HPS_IOB_2 |
NAND_WE_N | NAND Write Enable 这是一个低电平有效(active-low)信号。 |
输出 | HPS_IOA_3 | HPS_IOB_3 |
NAND_RE_N | NAND Read Enable 这是一个低电平有效(active-low)信号。 |
输出 | HPS_IOA_4 | HPS_IOB_4 |
NAND_WP_N | NAND Write Protect | 输出 | HPS_IOA_5 | HPS_IOB_5 |
NAND_ADQ2 | NAND Data Bit 2 | I/O | HPS_IOA_6 | HPS_IOB_6 |
NAND_ADQ3 | NAND Data Bit 3 | I/O | HPS_IOA_7 | HPS_IOB_7 |
NAND_CLE | NAND Command Latch Enable | 输出 | HPS_IOA_8 | HPS_IOB_8 |
NAND_ADQ4 | NAND Data Bit 4 | I/O | HPS_IOA_9 | HPS_IOB_9 |
NAND_ADQ5 | NAND Data Bit 5 | I/O | HPS_IOA_10 | HPS_IOB_10 |
NAND_ADQ6 | NAND Data Bit 6 | I/O | HPS_IOA_11 | HPS_IOB_11 |
NAND_ADQ7 | NAND Data Bit 7 | I/O | HPS_IOA_12 | HPS_IOB_12 |
NAND_ALE | NAND Address Latch Enable | 输出 | HPS_IOA_13 | HPS_IOB_13 |
NAND_RB | NAND Ready/Busy 通过一个上拉电阻将此管脚连接到VCCIO_HPS。关于上拉电阻值的更多信息,请参考NAND闪存规范。 |
输入 | HPS_IOA_14 | HPS_IOB_14 |
NAND_CE_N | NAND Chip Enable 这是一个低电平有效(active-low)信号。 |
输出 | HPS_IOA_15 | HPS_IOB_15 |
NAND_ADQ8 | NAND Data Bit 8 | I/O | HPS_IOA_17 | HPS_IOB_17 |
NAND_ADQ9 | NAND Data Bit 9 | I/O | HPS_IOA_18 | HPS_IOB_18 |
NAND_ADQ10 | NAND Data Bit 10 | I/O | HPS_IOA_19 | HPS_IOB_19 |
NAND_ADQ11 | NAND Data Bit 11 | I/O | HPS_IOA_20 | HPS_IOB_20 |
NAND_ADQ12 | NAND Data Bit 12 | I/O | HPS_IOA_21 | HPS_IOB_21 |
NAND_ADQ13 | NAND Data Bit 13 | I/O | HPS_IOA_22 | HPS_IOB_22 |
NAND_ADQ14 | NAND Data Bit 14 | I/O | HPS_IOA_23 | HPS_IOB_23 |
NAND_ADQ15 | NAND Data Bit 15 | I/O | HPS_IOA_24 | HPS_IOB_24 |