Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide

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ID 851698
Date 9/02/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Ashling* RiscFree* Integrated Development Environment (IDE) 2.3.4. Installing the USB-Blaster III Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Board 3.3. Modes of Operations 3.4. Performing Board Restore
3.4. Performing Board Restore x
3.4.1. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA C-Series Development Kit 3.4.2. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit 3.4.3. Restoring SD Card with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. BTS Functionalities
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Setting Up the Quartus® Prime Software for BTS Operation 4.1.2. Running the BTS GUI
4.2. BTS Functionalities x
4.2.1. The Agilex™ 3 FPGA Functionality 4.2.2. Other Functionalities
4.2.1. The Agilex™ 3 FPGA Functionality x
4.2.1.1. The Configure Menu 4.2.1.2. The GPIO Tab 4.2.1.3. The Memory Tab 4.2.1.4. The Transceiver Tab
4.2.1.2. The GPIO Tab x
4.2.1.2.1. The LED Tab 4.2.1.2.2. The Push Button Tab 4.2.1.2.3. The I2C Bus Tab
4.2.1.3. The Memory Tab x
4.2.1.3.1. The Fabric COMP Tab 4.2.1.3.2. The HPS/Fabric COMP Tab
4.2.1.4. The Transceiver Tab x
4.2.1.4.1. The DP Tab
4.2.2. Other Functionalities x
4.2.2.1. The Bottom Information Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview and Components A.2. Input and Output Components A.3. Components and Interfaces A.4. Clock Circuits A.5. System Power A.6. Power Guidelines A.7. Power Distribution System A.8. Expansion Boards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
A.2. Input and Output Components x
A.2.1. Push Buttons A.2.2. Switches A.2.3. LEDs
A.3. Components and Interfaces x
A.3.1. PCI Express* ( PCIe* ) Interface A.3.2. DisplayPort Interface A.3.3. MIPI Interface A.3.4. LPDDR4 Interfaces A.3.5. Raspberry Pi* , Pmod, and PCIe* x1 Interfaces A.3.6. HPS I/O48 Interface A.3.7. I2C
A.6. Power Guidelines x
A.6.1. Primary Mode—As a Standalone Evaluation Board A.6.2. Optional Mode—As a PCIe* Add-in Card in PCIe* Host System
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

3.2. Powering Up the Development Board

The Agilex™ 3 FPGA/FPGA and SoC C-Series development board is designed to be powered by a standard USB-PD Type-C compliant power adapter capable of providing a minimum of 27 W.

Depending on the FPGA workload, you need a USB-PD adapter that can supply higher power. As a recommendation, a typical 65 W USB-PD power adapter used for powering laptops is more than sufficient to fully power the Agilex™ 3 FPGA/FPGA and SoC C-Series development board for all use cases. Lower USB-PD power adapters can be used for lower power designs.

Note: You must provide a USB-PD Type-C power adapter as it is not supplied with the development kits.

Recommended power adapter:

  • Lenovo 65W AC adapter
  • Model No: ADLX65YSCC3A
To power up the development board:
  1. Connect the USB Type-C end of the USB-PD power adapter to the left edge of the board's USB Type-C mating connector (J8), and connect the other end of the USB-PD adapter to an appropriate wall power outlet.
  2. For the Agilex™ 3 FPGA and SoC C-Series Development Kit, connect the Type-C cable from the USB Type-C connector J2 to the host PC.
  3. For the Agilex™ 3 FPGA and SoC C-Series Development Kit, launch the UART terminal application on the host PC, and follow the setting list:
    • Speed: 115200
    • Data: 8 bit
    • Parity: none
    • Stop bits: 1 bit
    • Flow control: none
  4. Set the power switch SW3 (located next to the J8 power connector) to the ON position to turn on the board.
  5. When powered on, observe that the board's POWER GOOD green LED (D17) is turned on. If this LED blinks RED, it indicates that the USB-PD power adapter is incompatible with the board. In this event, replace the USB-PD power adapter with a compatible one and try again.

When powered on, the board negotiates an appropriate power contract with the USB-PD adapter. Depending on the capabilities of the USB-PD adapter, an input voltage of 9 V to 20 V is applied to the board.

A successfully negotiated power contract turns on the green POWER GOOD LED. For USB power adapters that are not PD compliant or have insufficient power, the board does not power on and instead the red CAPABILITIES MISMATCH LED blinks or does not turn on. The POWER GOOD and CAPABILITIES MISMATCH LED (D17) are located next to the power switch (SW3).

Figure 7. Powering the Agilex™ 3 FPGA/FPGA and SoC C-Series Development Board

After the POWER GOOD green LED turns on, you can observe the functionality of the development kits:

  • On the Agilex™ 3 FPGA C-Series Development Kit, the QSPI flash is pre-programmed with GPIO image. When powered on, observe that LED D9 is blinking. For more GPIO functions, refer to the The GPIO Tab section.
  • On the Agilex™ 3 FPGA and SoC C-Series Development Kit, the QSPI flash is pre-programmed with GHRD image. When powered on, observe the HPS boot-up on the UART terminal.
Figure 8. Linux Log with Username

After Linux boots up, log in using root as username, no password is required.

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