Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide

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ID 851698
Date 9/02/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Ashling* RiscFree* Integrated Development Environment (IDE) 2.3.4. Installing the USB-Blaster III Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Board 3.3. Modes of Operations 3.4. Performing Board Restore
3.4. Performing Board Restore x
3.4.1. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA C-Series Development Kit 3.4.2. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit 3.4.3. Restoring SD Card with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. BTS Functionalities
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Setting Up the Quartus® Prime Software for BTS Operation 4.1.2. Running the BTS GUI
4.2. BTS Functionalities x
4.2.1. The Agilex™ 3 FPGA Functionality 4.2.2. Other Functionalities
4.2.1. The Agilex™ 3 FPGA Functionality x
4.2.1.1. The Configure Menu 4.2.1.2. The GPIO Tab 4.2.1.3. The Memory Tab 4.2.1.4. The Transceiver Tab
4.2.1.2. The GPIO Tab x
4.2.1.2.1. The LED Tab 4.2.1.2.2. The Push Button Tab 4.2.1.2.3. The I2C Bus Tab
4.2.1.3. The Memory Tab x
4.2.1.3.1. The Fabric COMP Tab 4.2.1.3.2. The HPS/Fabric COMP Tab
4.2.1.4. The Transceiver Tab x
4.2.1.4.1. The DP Tab
4.2.2. Other Functionalities x
4.2.2.1. The Bottom Information Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview and Components A.2. Input and Output Components A.3. Components and Interfaces A.4. Clock Circuits A.5. System Power A.6. Power Guidelines A.7. Power Distribution System A.8. Expansion Boards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
A.2. Input and Output Components x
A.2.1. Push Buttons A.2.2. Switches A.2.3. LEDs
A.3. Components and Interfaces x
A.3.1. PCI Express* ( PCIe* ) Interface A.3.2. DisplayPort Interface A.3.3. MIPI Interface A.3.4. LPDDR4 Interfaces A.3.5. Raspberry Pi* , Pmod, and PCIe* x1 Interfaces A.3.6. HPS I/O48 Interface A.3.7. I2C
A.6. Power Guidelines x
A.6.1. Primary Mode—As a Standalone Evaluation Board A.6.2. Optional Mode—As a PCIe* Add-in Card in PCIe* Host System
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

3.1. Default Settings

The Agilex™ 3 FPGA/FPGA and SoC C-Series development kit ships with its board switches and jumpers preconfigured to support the design examples in the kit. If you suspect your board might not be correctly configured with the default settings, follow the instructions in the factory default switch and jumper settings table to return to its factory settings before proceeding ahead.

Table 4.  Factory Default Switch and Jumper Settings
Note: Do not set the switches when the power is on. Only set the switches after the power is off.
Switch Default Position Function
SW3 OFF

Board slide power switch

  • Slide SW3 to the ON position to power on the board
  • Slide SW3 to the OFF position to power off the board
SW4[1:4] OFF/OFF/OFF/OFF

Board configuration DIP switch SW4.1

  • OFF—Sets the board to function as a PCIe* End Point
  • ON—Sets the board to function as a PCIe* Root Port

Board configuration DIP switch SW4.2

  • OFF—Enables the -0.5% spread spectrum modulation for the PCIe* clock
  • ON—Disables the -0.5% spread spectrum modulation for the PCIe* clock

Board configuration DIP switch SW4.3

  • OFF—Connects a 100 MHz clock to the HVIO bank 5B, pin AJ27
  • ON—Connects the Raspberry Pi* GPIO26 to HVIO bank 5B, pin AJ27

SW4.4

  • OFF—Sets the FPGA to load the user application image from the QSPI flash
  • ON—Sets the FPGA to load the factory recover image from the QSPI flash
Note: Current Altera designs do not use SW4.4. You can include this switch in your design, depending on your application needs.
S1 OFF

HPS COLD RESET tactile push button

  • Pushing and releasing S1 generates a 20 ms active low pulse to the HPS_COLD_RESETn input of the FPGA
S2 OFF

Dedicated general-purpose tactile push button for the HPS interface

  • Pushing this button drives the HPS push button input logic low
  • Releasing this button drives the HPS push button input logic high
S3 OFF

USER dedicated general-purpose tactile push button (PB1/FPGA_RSTN) connected to HSIO bank 3A, pin M1. This button can be used as a general-purpose push button or as a FPGA RESET push button for user designs.

  • Pushing this button drives the USER push button PB1/FPGA_RSTN input logic low
  • Releasing this button drives the USER push button PB1/FPGA_RSTN input logic high
S4 OFF

USER dedicated general-purpose tactile push button (PB0) connected to HSIO bank 3A, pin L1

  • Pushing this button drives the USER push button PB0 input logic low
  • Releasing this button drives the USER push button PB0 input logic high
J17 OPEN

Voltage selection jumper for HVIO bank 5A

  • Shunting J17 sets the HVIO bank 5A voltage to 1.8 V
  • Leaving J17 open sets the HVIO bank 5A voltage to 3.3 V

You must use this jumper to set the HVIO 5A bank voltage (either 1.8 V or 3.3 V) to match the voltage of the expansion daughter card that is plugged into Raspberry Pi* connector (J14) or Pmod expansion connector (J1).

Failure to set the proper bank voltage can cause damage to the development kit and any attached Raspberry Pi* /Pmod expansion boards.

The default HVIO 5A bank voltage is set to 3.3 V (no shunt on J17).
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