Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide

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ID 851698
Date 9/02/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Ashling* RiscFree* Integrated Development Environment (IDE) 2.3.4. Installing the USB-Blaster III Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Board 3.3. Modes of Operations 3.4. Performing Board Restore
3.4. Performing Board Restore x
3.4.1. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA C-Series Development Kit 3.4.2. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit 3.4.3. Restoring SD Card with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. BTS Functionalities
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Setting Up the Quartus® Prime Software for BTS Operation 4.1.2. Running the BTS GUI
4.2. BTS Functionalities x
4.2.1. The Agilex™ 3 FPGA Functionality 4.2.2. Other Functionalities
4.2.1. The Agilex™ 3 FPGA Functionality x
4.2.1.1. The Configure Menu 4.2.1.2. The GPIO Tab 4.2.1.3. The Memory Tab 4.2.1.4. The Transceiver Tab
4.2.1.2. The GPIO Tab x
4.2.1.2.1. The LED Tab 4.2.1.2.2. The Push Button Tab 4.2.1.2.3. The I2C Bus Tab
4.2.1.3. The Memory Tab x
4.2.1.3.1. The Fabric COMP Tab 4.2.1.3.2. The HPS/Fabric COMP Tab
4.2.1.4. The Transceiver Tab x
4.2.1.4.1. The DP Tab
4.2.2. Other Functionalities x
4.2.2.1. The Bottom Information Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview and Components A.2. Input and Output Components A.3. Components and Interfaces A.4. Clock Circuits A.5. System Power A.6. Power Guidelines A.7. Power Distribution System A.8. Expansion Boards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
A.2. Input and Output Components x
A.2.1. Push Buttons A.2.2. Switches A.2.3. LEDs
A.3. Components and Interfaces x
A.3.1. PCI Express* ( PCIe* ) Interface A.3.2. DisplayPort Interface A.3.3. MIPI Interface A.3.4. LPDDR4 Interfaces A.3.5. Raspberry Pi* , Pmod, and PCIe* x1 Interfaces A.3.6. HPS I/O48 Interface A.3.7. I2C
A.6. Power Guidelines x
A.6.1. Primary Mode—As a Standalone Evaluation Board A.6.2. Optional Mode—As a PCIe* Add-in Card in PCIe* Host System
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.3.3. MIPI Interface

The Agilex™ 3 FPGA/FPGA and SoC C-Series development board provides two FPC MIPI interface connected to HSIO banks 2A and 3A.
Table 22.  MIPI Bank 2A
Schematic Signal Name FPGA Pin Number I/O Standard Description
MIPI_CONN_2A_CAM_D3_P R1 1.1 V MIPI bank 2A data 3 (true)
MIPI_CONN_2A_CAM_D3_N P2 1.1 V MIPI bank 2A data 3 (compliment)
MIPI_CONN_2A_CAM_D2_P R2 1.1 V MIPI bank 2A data 2 (true)
MIPI_CONN_2A_CAM_D2_N T1 1.1 V MIPI bank 2A data 2 (compliment)
MIPI_CONN_2A_CAM_D1_P V2 1.1 V MIPI bank 2A data 1 (true)
MIPI_CONN_2A_CAM_D1_N V2 1.1 V MIPI bank 2A data 1 (compliment)
MIPI_CONN_2A_CAM_D0_P Y1 1.1 V MIPI bank 2A data 0 (true)
MIPI_CONN_2A_CAM_D0_N W2 1.1 V MIPI bank 2A data 0 (compliment)
MIPI_CONN_2A_CAM_CK_P T2 1.1 V MIPI bank 2A clock (true)
MIPI_CONN_2A_CAM_CK_N U1 1.1 V MIPI bank 2A clock (compliment)
Table 23.  MIPI Bank 3A
Schematic Signal Name FPGA Pin Number I/O Standard Description
MIPI_CONN_3A_CAM_D3_P G3 1.1 V MIPI bank 3A data 3 (true)
MIPI_CONN_3A_CAM_D3_N F3 1.1 V MIPI bank 3A data 3 (compliment)
MIPI_CONN_3A_CAM_D2_P F4 1.1 V MIPI bank 3A data 2 (true)
MIPI_CONN_3A_CAM_D2_N E4 1.1 V MIPI bank 3A data 2 (compliment)
MIPI_CONN_3A_CAM_D1_P F6 1.1 V MIPI bank 3A data 1 (true)
MIPI_CONN_3A_CAM_D1_N E6 1.1 V MIPI bank 3A data 1 (compliment)
MIPI_CONN_3A_CAM_D0_P C5 1.1 V MIPI bank 3A data 0 (true)
MIPI_CONN_3A_CAM_D0_N D4 1.1 V MIPI bank 3A data 0 (compliment)
MIPI_CONN_3A_CAM_CK_P D5 1.1 V MIPI bank 3A clock (true)
MIPI_CONN_3A_CAM_CK_N E5 1.1 V MIPI bank 3A clock (compliment)
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