Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide

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ID 851698
Date 9/02/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Ashling* RiscFree* Integrated Development Environment (IDE) 2.3.4. Installing the USB-Blaster III Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Board 3.3. Modes of Operations 3.4. Performing Board Restore
3.4. Performing Board Restore x
3.4.1. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA C-Series Development Kit 3.4.2. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit 3.4.3. Restoring SD Card with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. BTS Functionalities
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Setting Up the Quartus® Prime Software for BTS Operation 4.1.2. Running the BTS GUI
4.2. BTS Functionalities x
4.2.1. The Agilex™ 3 FPGA Functionality 4.2.2. Other Functionalities
4.2.1. The Agilex™ 3 FPGA Functionality x
4.2.1.1. The Configure Menu 4.2.1.2. The GPIO Tab 4.2.1.3. The Memory Tab 4.2.1.4. The Transceiver Tab
4.2.1.2. The GPIO Tab x
4.2.1.2.1. The LED Tab 4.2.1.2.2. The Push Button Tab 4.2.1.2.3. The I2C Bus Tab
4.2.1.3. The Memory Tab x
4.2.1.3.1. The Fabric COMP Tab 4.2.1.3.2. The HPS/Fabric COMP Tab
4.2.1.4. The Transceiver Tab x
4.2.1.4.1. The DP Tab
4.2.2. Other Functionalities x
4.2.2.1. The Bottom Information Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview and Components A.2. Input and Output Components A.3. Components and Interfaces A.4. Clock Circuits A.5. System Power A.6. Power Guidelines A.7. Power Distribution System A.8. Expansion Boards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
A.2. Input and Output Components x
A.2.1. Push Buttons A.2.2. Switches A.2.3. LEDs
A.3. Components and Interfaces x
A.3.1. PCI Express* ( PCIe* ) Interface A.3.2. DisplayPort Interface A.3.3. MIPI Interface A.3.4. LPDDR4 Interfaces A.3.5. Raspberry Pi* , Pmod, and PCIe* x1 Interfaces A.3.6. HPS I/O48 Interface A.3.7. I2C
A.6. Power Guidelines x
A.6.1. Primary Mode—As a Standalone Evaluation Board A.6.2. Optional Mode—As a PCIe* Add-in Card in PCIe* Host System
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.3.4. LPDDR4 Interfaces

The Agilex™ 3 FPGA/FPGA and SoC C-Series development board provides two LPDDR4 x32 interfaces connected to the FPGA at banks 2A and 3A.
Table 24.  LPDDR4 Bank 2A Pin Assignments
Schematic Signal Name FPGA Pin Number I/O Standard Description
LP4_2A_CA0 AF7 1.1 V LPDDR4 memory command/address 0
LP4_2A_CA1 AE7 1.1 V LPDDR4 memory command/address 1
LP4_2A_CA2 AF6 1.1 V LPDDR4 memory command/address 2
LP4_2A_CA3 AE6 1.1 V LPDDR4 memory command/address 3
LP4_2A_CA4 AH5 1.1 V LPDDR4 memory command/address 4
LP4_2A_CA5 AG5 1.1 V LPDDR4 memory command/address 5
LP4_2A_CKE_R0 AH6 1.1 V LPDDR4 memory clock enable
LP4_2A_CS_N0 AF4 1.1 V LPDDR4 memory chip select
LP4_2A_REFCLK_P AF3 1.1 V LPDDR4 memory FPGA reference clock (true)
LP4_2A_REFCLK_N AE4 1.1 V LPDDR4 memory FPGA reference clock (compliment)
LP4_2A_RESET_N AD4 1.1 V LPDDR4 memory reset
LP4_2A_CK_P AB3 1.1 V LPDDR4 memory clock (true)
LP4_2A_CK_N AA4 1.1 V LPDDR4 memory clock (compliment)
RZQ_B_2A_R AD3 N/A LPDDR4 RZQ
LP4_2A_DQ0 AB1 1.1 V LPDDR4 memory data 0
LP4_2A_DQ1 AA2 1.1 V LPDDR4 memory data 1
LP4_2A_DQ2 AA1 1.1 V LPDDR4 memory data 2
LP4_2A_DQ3 Y2 1.1 V LPDDR4 memory data 3
LP4_2A_DQ4 AG1 1.1 V LPDDR4 memory data 4
LP4_2A_DQ5 AF2 1.1 V LPDDR4 memory data 5
LP4_2A_DQ6 AF1 1.1 V LPDDR4 memory data 6
LP4_2A_DQ7 AE2 1.1 V LPDDR4 memory data 7
LP4_2A_DM0 AD2 1.1 V LPDDR4 memory data mask 0
LP4_2A_DQS_P0 AC1 1.1 V LPDDR4 memory data strobe 0 (True)
LP4_2A_DQS_N0 AD2 1.1 V LPDDR4 memory data strobe 0 (Compliment)
LP4_2A_DQ8 AK6 1.1 V LPDDR4 memory data 8
LP4_2A_DQ9 AK7 1.1 V LPDDR4 memory data 9
LP4_2A_DQ10 AJ7 1.1 V LPDDR4 memory data 10
LP4_2A_DQ11 AJ8 1.1 V LPDDR4 memory data 11
LP4_2A_DQ12 AG3 1.1 V LPDDR4 memory data 12
LP4_2A_DQ13 AH2 1.1 V LPDDR4 memory data 13
LP4_2A_DQ14 AH3 1.1 V LPDDR4 memory data 14
LP4_2A_DQ15 AJ3 1.1 V LPDDR4 memory data 15
LP4_2A_DM1 AJ5 1.1 V LPDDR4 memory data mask 1
LP4_2A_DQS_P1 AK4 1.1 V LPDDR4 memory data strobe 1 (True)
LP4_2A_DQS_N1 AJ4 1.1 V LPDDR4 memory data strobe 1 (Compliment)
LP4_2A_DQ16 P4 1.1 V LPDDR4 memory data 16
LP4_2A_DQ17 P5 1.1 V LPDDR4 memory data 17
LP4_2A_DQ18 U3 1.1 V LPDDR4 memory data 18
LP4_2A_DQ19 V3 1.1 V LPDDR4 memory data 19
LP4_2A_DQ20 W3 1.1 V LPDDR4 memory data 20
LP4_2A_DQ21 U4 1.1 V LPDDR4 memory data 21
LP4_2A_DQ22 P3 1.1 V LPDDR4 memory data 22
LP4_2A_DQ23 N3 1.1 V LPDDR4 memory data 23
LP4_2A_DM2 T3 1.1 V LPDDR4 memory data mask 2
LP4_2A_DQS_P2 U5 1.1 V LPDDR4 memory data strobe 2 (True)
LP4_2A_DQS_N2 T4 1.1 V LPDDR4 memory data strobe 2 (Compliment)
LP4_2A_DQ24 V5 1.1 V LPDDR4 memory data 24
LP4_2A_DQ25 V6 1.1 V LPDDR4 memory data 25
LP4_2A_DQ26 N7 1.1 V LPDDR4 memory data 26
LP4_2A_DQ27 N6 1.1 V LPDDR4 memory data 27
LP4_2A_DQ28 R7 1.1 V LPDDR4 memory data 28
LP4_2A_DQ29 P7 1.1 V LPDDR4 memory data 29
LP4_2A_DQ30 W5 1.1 V LPDDR4 memory data 30
LP4_2A_DQ31 U6 1.1 V LPDDR4 memory data 31
LP4_2A_DM3 T6 1.1 V LPDDR4 memory data mask 3
LP4_2A_DQS_P3 R5 1.1 V LPDDR4 memory data strobe 3 (True)
LP4_2A_DQS_N3 R6 1.1 V LPDDR4 memory data strobe 3 (Compliment)
Table 25.  LPDDR4 Bank 3A Pin Assignments
Schematic Signal Name FPGA Pin Number I/O Standard Description
LP4_3A_CA0 C2 1.1 V LPDDR4 memory command/address 0
LP4_3A_CA1 D3 1.1 V LPDDR4 memory strobe/address 1
LP4_3A_CA2 C3 1.1 V LPDDR4 memory strobe/address 2
LP4_3A_CA3 B3 1.1 V LPDDR4 memory strobe/address 3
LP4_3A_CA4 A6 1.1 V LPDDR4 memory strobe/address 4
LP4_3A_CA5 B5 1.1 V LPDDR4 memory strobe/address 5
LP4_3A_CKE_R0 A4 1.1 V LPDDR4 memory data enable
LP4_3A_CS_N0 C7 1.1 V LPDDR4 memory chip select
LP4_3A_REFCLK_P A7 1.1 V LPDDR4 memory FPGA reference data (true)
LP4_3A_REFCLK_N B6 1.1 V LPDDR4 memory FPGA reference data (compliment)
LP4_3A_RESET_N E15 1.1 V LPDDR4 memory reset
LP4_3A_CK_P E9 1.1 V LPDDR4 memory data (true)
LP4_3A_CK_N E10 1.1 V LPDDR4 memory data (compliment)
RZQ_B_3A_R E14 N/A LPDDR4 RZQ
LP4_3A_DQ0 H6 1.1 V LPDDR4 memory data 0
LP4_3A_DQ1 H7 1.1 V LPDDR4 memory data 1
LP4_3A_DQ2 G5 1.1 V LPDDR4 memory data 2
LP4_3A_DQ3 G6 1.1 V LPDDR4 memory data 3
LP4_3A_DQ4 M6 1.1 V LPDDR4 memory data 4
LP4_3A_DQ5 N5 1.1 V LPDDR4 memory data 5
LP4_3A_DQ6 M6 1.1 V LPDDR4 memory data 6
LP4_3A_DQ7 L6 1.1 V LPDDR4 memory data 7
LP4_3A_DM0 L7 1.1 V LPDDR4 memory data mask 0
LP4_3A_DQS_P0 K7 1.1 V LPDDR4 memory data strobe 0 (True)
LP4_3A_DQS_N0 J7 1.1 V LPDDR4 memory data strobe 0 (Compliment)
LP4_3A_DQ8 L3 1.1 V LPDDR4 memory data 8
LP4_3A_DQ9 J5 1.1 V LPDDR4 memory data 9
LP4_3A_DQ10 M3 1.1 V LPDDR4 memory data 10
LP4_3A_DQ11 L4 1.1 V LPDDR4 memory data 11
LP4_3A_DQ12 M4 1.1 V LPDDR4 memory data 12
LP4_3A_DQ13 G4 1.1 V LPDDR4 memory data 13
LP4_3A_DQ14 H3 1.1 V LPDDR4 memory data 14
LP4_3A_DQ15 H5 1.1 V LPDDR4 memory data 15
LP4_3A_DM1 K5 1.1 V LPDDR4 memory data mask 1
LP4_3A_DQS_P1 J4 1.1 V LPDDR4 memory data strobe 1 (True)
LP4_3A_DQS_N1 J3 1.1 V LPDDR4 memory data strobe 1 (Compliment)
LP4_3A_DQ16 D15 1.1 V LPDDR4 memory data 16
LP4_3A_DQ17 C13 1.1 V LPDDR4 memory data 17
LP4_3A_DQ18 C10 1.1 V LPDDR4 memory data 18
LP4_3A_DQ19 D10 1.1 V LPDDR4 memory data 19
LP4_3A_DQ20 C8 1.1 V LPDDR4 memory data 20
LP4_3A_DQ21 D9 1.1 V LPDDR4 memory data 21
LP4_3A_DQ22 D14 1.1 V LPDDR4 memory data 22
LP4_3A_DQ23 C15 1.1 V LPDDR4 memory data 23
LP4_3A_DM2 D13 1.1 V LPDDR4 memory data mask 2
LP4_3A_DQS_P2 D12 1.1 V LPDDR4 memory data strobe 2 (True)
LP4_3A_DQS_N2 C11 1.1 V LPDDR4 memory data strobe 2 (Compliment)
LP4_3A_DQ24 A8 1.1 V LPDDR4 memory data 24
LP4_3A_DQ25 B8 1.1 V LPDDR4 memory data 25
LP4_3A_DQ26 A9 1.1 V LPDDR4 memory data 26
LP4_3A_DQ27 B9 1.1 V LPDDR4 memory data 27
LP4_3A_DQ28 B13 1.1 V LPDDR4 memory data 28
LP4_3A_DQ29 A13 1.1 V LPDDR4 memory data 29
LP4_3A_DQ30 B14 1.1 V LPDDR4 memory data 30
LP4_3A_DQ31 A14 1.1 V LPDDR4 memory data 31
LP4_3A_DM3 B11 1.1 V LPDDR4 memory data mask 3
LP4_3A_DQS_P3 B10 1.1 V LPDDR4 memory data strobe 3 (True)
LP4_3A_DQS_N3 A11 1.1 V LPDDR4 memory data strobe 3 (Compliment)
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