Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide
ID
851698
Date
9/02/2025
Public
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information
3.4.1. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA C-Series Development Kit
3.4.2. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit
3.4.3. Restoring SD Card with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit
6.1. Golden Top
You can use the Golden Top project as the starting point for your designs. It comes loaded with constraints, pin locations, define I/O standard, direction and general termination.
- Define a macro to enable or disable the corresponding interface in the top-level design entity, and the interfaces that require IP connection are disabled by default.
- Open the macro according to the requirements. If the pins are not connected to the IP, a fitter error occurs.