Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide

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ID 851698
Date 9/02/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Ashling* RiscFree* Integrated Development Environment (IDE) 2.3.4. Installing the USB-Blaster III Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Board 3.3. Modes of Operations 3.4. Performing Board Restore
3.4. Performing Board Restore x
3.4.1. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA C-Series Development Kit 3.4.2. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit 3.4.3. Restoring SD Card with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. BTS Functionalities
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Setting Up the Quartus® Prime Software for BTS Operation 4.1.2. Running the BTS GUI
4.2. BTS Functionalities x
4.2.1. The Agilex™ 3 FPGA Functionality 4.2.2. Other Functionalities
4.2.1. The Agilex™ 3 FPGA Functionality x
4.2.1.1. The Configure Menu 4.2.1.2. The GPIO Tab 4.2.1.3. The Memory Tab 4.2.1.4. The Transceiver Tab
4.2.1.2. The GPIO Tab x
4.2.1.2.1. The LED Tab 4.2.1.2.2. The Push Button Tab 4.2.1.2.3. The I2C Bus Tab
4.2.1.3. The Memory Tab x
4.2.1.3.1. The Fabric COMP Tab 4.2.1.3.2. The HPS/Fabric COMP Tab
4.2.1.4. The Transceiver Tab x
4.2.1.4.1. The DP Tab
4.2.2. Other Functionalities x
4.2.2.1. The Bottom Information Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview and Components A.2. Input and Output Components A.3. Components and Interfaces A.4. Clock Circuits A.5. System Power A.6. Power Guidelines A.7. Power Distribution System A.8. Expansion Boards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
A.2. Input and Output Components x
A.2.1. Push Buttons A.2.2. Switches A.2.3. LEDs
A.3. Components and Interfaces x
A.3.1. PCI Express* ( PCIe* ) Interface A.3.2. DisplayPort Interface A.3.3. MIPI Interface A.3.4. LPDDR4 Interfaces A.3.5. Raspberry Pi* , Pmod, and PCIe* x1 Interfaces A.3.6. HPS I/O48 Interface A.3.7. I2C
A.6. Power Guidelines x
A.6.1. Primary Mode—As a Standalone Evaluation Board A.6.2. Optional Mode—As a PCIe* Add-in Card in PCIe* Host System
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

3.3. Modes of Operations

The Agilex™ 3 FPGA/FPGA and SoC C-Series development board is designed to operate in two main modes—in bench-top mode and as a PCIe* add-in card.

In Bench-Top Mode (Default Mode)

You only need to connect a USB-PD compliant power adapter to J8 to power on the board and run the example designs included in the development kit. The example designs allow you to evaluate the functionality of various provided features of this development kit. In this mode, you can also use the Agilex™ 3 FPGA/FPGA and SoC C-Series development board to interface with and create custom FPGA designs for various Raspberry Pi* 4/5 HAT boards and Digilent Pmod* (peripheral module) boards for those respective ecosystems.
Note: The Raspberry Pi* HAT board and Digilent Pmod peripherals share the same HVIO banks so only one add-in board can be used at a time.
Figure 9. Optional Raspberry Pi* HAT and Digilent Pmod Boards Attached

As a PCIe* Add-in Card

To convert the Agilex™ 3 FPGA/FPGA and SoC C-Series development board into a PCIe* add-in card, you must purchase the optional Altera PCIe* 3.0 x1 gold finger daughter card and mount it to this board. The PCIe* gold finger daughter card kit includes the PCIe* I/O bracket and all necessary hardware to convert the Agilex™ 3 FPGA/FPGA and SoC C-Series development board into a PCIe* add-in card.
Note: Power for the development kit must still be provided by the USB-PD power adapter because the Altera PCIe* 3.0 x1 gold finger daughter card does not pass power from the PCIe* slot to power the Agilex™ 3 FPGA/FPGA and SoC C-Series development board.
Table 5.  Available PCIe* Daughter Cards
Model Compatible Development Kit
DC-A3PCIE
  • DK-A3Y135BM16AEA
DC-A3SOCPCIE
  • DK-A3W135BM16AEA
  • DK-A3Y135BM16AEA
Figure 10. Optional Altera PCIe* 3.0 x1 Gold Finger Daughter Board and PCIe* I/O Bracket Attached
When operating the card in a PCIe* system, insert the card into an available PCIe* slot and connect a USB-PD compliant power to connector J8 as described previously. All power for the Agilex™ 3 FPGA and SoC C-Series Development Kits are derived from the external USB-PD power supply.
Note:
  1. When operating as a PCIe* add-in card, the board does not power on unless power is supplied to J8 and switch SW3 is ON as described previously.
  2. When operating as a PCIe* add-in card, Altera does not recommend that you attach a Raspberry Pi* HAT because the added height of the HAT board can interfere with the adjacent PCIe* cards in the PCIe* system.
  3. When used as a PCIe* add-in card inserted into a PCIe* server, Altera does not recommend that you attach additional PCIe* cards in adjacent slots of the same server. This is because overcrowding between two adjacent PCIe* daughter cards may affect signal performance.
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