Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide

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ID 851698
Date 9/02/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Ashling* RiscFree* Integrated Development Environment (IDE) 2.3.4. Installing the USB-Blaster III Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Board 3.3. Modes of Operations 3.4. Performing Board Restore
3.4. Performing Board Restore x
3.4.1. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA C-Series Development Kit 3.4.2. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit 3.4.3. Restoring SD Card with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. BTS Functionalities
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Setting Up the Quartus® Prime Software for BTS Operation 4.1.2. Running the BTS GUI
4.2. BTS Functionalities x
4.2.1. The Agilex™ 3 FPGA Functionality 4.2.2. Other Functionalities
4.2.1. The Agilex™ 3 FPGA Functionality x
4.2.1.1. The Configure Menu 4.2.1.2. The GPIO Tab 4.2.1.3. The Memory Tab 4.2.1.4. The Transceiver Tab
4.2.1.2. The GPIO Tab x
4.2.1.2.1. The LED Tab 4.2.1.2.2. The Push Button Tab 4.2.1.2.3. The I2C Bus Tab
4.2.1.3. The Memory Tab x
4.2.1.3.1. The Fabric COMP Tab 4.2.1.3.2. The HPS/Fabric COMP Tab
4.2.1.4. The Transceiver Tab x
4.2.1.4.1. The DP Tab
4.2.2. Other Functionalities x
4.2.2.1. The Bottom Information Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview and Components A.2. Input and Output Components A.3. Components and Interfaces A.4. Clock Circuits A.5. System Power A.6. Power Guidelines A.7. Power Distribution System A.8. Expansion Boards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
A.2. Input and Output Components x
A.2.1. Push Buttons A.2.2. Switches A.2.3. LEDs
A.3. Components and Interfaces x
A.3.1. PCI Express* ( PCIe* ) Interface A.3.2. DisplayPort Interface A.3.3. MIPI Interface A.3.4. LPDDR4 Interfaces A.3.5. Raspberry Pi* , Pmod, and PCIe* x1 Interfaces A.3.6. HPS I/O48 Interface A.3.7. I2C
A.6. Power Guidelines x
A.6.1. Primary Mode—As a Standalone Evaluation Board A.6.2. Optional Mode—As a PCIe* Add-in Card in PCIe* Host System
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.3.2. DisplayPort Interface

The Agilex™ 3 FPGA/FPGA and SoC C-Series development board provides two DisplayPort v1.4 interfaces capable of operating at 8.1 Gbps per lane.

The transmit DisplayPort interface (J12) connects TX lanes 2 and 3 from the transceiver bank 1A. The receive DisplayPort interface (J16) connects RX lanes 2 and 3 from the transceiver bank 1A. In addition, the DisplayPort control signals and Auxiliary (AUX) channels connect to the HSIO banks 2A and 3A. The AUX channels are converted from differential to single ended signals for connection to the HSIO banks.

Table 21.  DisplayPort Pin Assignment
Schematic Signal Name FPGA Pin Number I/O Standard Description
DP_TX_0_DRV_DP K27 True Differential DisplayPort transmit data 0 (True)
DP_TX_0_DRV_DN J27 True Differential DisplayPort transmit data 0 (Compliment)
DP_TX_1_DRV_DP G27 True Differential DisplayPort transmit data 1 (True)
DP_TX_1_DRV_DN F27 True Differential DisplayPort transmit data 1 (Compliment)
DP_TX_CON_HPD_1V1 Y6 1.1 V DisplayPort transmit hot plug detect
DP_TX_CON_CONFIG1_1V1 W7 1.1 V DisplayPort transmit configuration 1
DP_TX_CON_CONFIG2_DRIVE_N_1V1 V7 1.1 V DisplayPort transmit configuration 2
DP_TX_AUX_DEV_OE_1V1 AB5 1.1 V DisplayPort TX AUX channel output enable
DP_TX_AUX_DEV_OUT_1V1 H2 1.1 V DisplayPort TX AUX channel write data
DP_TX_AUX_DEV_IN_1V1 J1 1.1 V DisplayPort TX AUX channel read data
DP_RX_0_DRV_DP F30 True Differential DisplayPort receive data 0 (True)
DP_RX_0_DRV_DN F29 True Differential DisplayPort receive data 0 (Compliment)
DP_RX_1_DRV_DP D30 True Differential DisplayPort receive data 1 (True)
DP_RX_1_DRV_DN D29 True Differential DisplayPort receive data 1 (Compliment)
DP_RX_CON_HPD_1V1 AB6 1.1 V DisplayPort receive hot plug detect
DP_RX_AUX_DEV_OE_1V1 Y7 1.1 V DisplayPort RX AUX channel output enable
DP_RX_AUX_DEV_OUT_1V1 K2 1.1 V DisplayPort RX AUX channel write data
DP_RX_AUX_DEV_IN_1V1 H1 1.1 V DisplayPort RX AUX channel read data
DP_RX_AUX_DP_SENSE_1V1 AA7 1.1 V DisplayPort RX AUX channel sense (true)
DP_RX_AUX_DN_SENSE_1V1 AA6 1.1 V DisplayPort RX AUX channel sense (compliment)
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