Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide

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ID 851698
Date 9/02/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Ashling* RiscFree* Integrated Development Environment (IDE) 2.3.4. Installing the USB-Blaster III Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Board 3.3. Modes of Operations 3.4. Performing Board Restore
3.4. Performing Board Restore x
3.4.1. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA C-Series Development Kit 3.4.2. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit 3.4.3. Restoring SD Card with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. BTS Functionalities
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Setting Up the Quartus® Prime Software for BTS Operation 4.1.2. Running the BTS GUI
4.2. BTS Functionalities x
4.2.1. The Agilex™ 3 FPGA Functionality 4.2.2. Other Functionalities
4.2.1. The Agilex™ 3 FPGA Functionality x
4.2.1.1. The Configure Menu 4.2.1.2. The GPIO Tab 4.2.1.3. The Memory Tab 4.2.1.4. The Transceiver Tab
4.2.1.2. The GPIO Tab x
4.2.1.2.1. The LED Tab 4.2.1.2.2. The Push Button Tab 4.2.1.2.3. The I2C Bus Tab
4.2.1.3. The Memory Tab x
4.2.1.3.1. The Fabric COMP Tab 4.2.1.3.2. The HPS/Fabric COMP Tab
4.2.1.4. The Transceiver Tab x
4.2.1.4.1. The DP Tab
4.2.2. Other Functionalities x
4.2.2.1. The Bottom Information Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview and Components A.2. Input and Output Components A.3. Components and Interfaces A.4. Clock Circuits A.5. System Power A.6. Power Guidelines A.7. Power Distribution System A.8. Expansion Boards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
A.2. Input and Output Components x
A.2.1. Push Buttons A.2.2. Switches A.2.3. LEDs
A.3. Components and Interfaces x
A.3.1. PCI Express* ( PCIe* ) Interface A.3.2. DisplayPort Interface A.3.3. MIPI Interface A.3.4. LPDDR4 Interfaces A.3.5. Raspberry Pi* , Pmod, and PCIe* x1 Interfaces A.3.6. HPS I/O48 Interface A.3.7. I2C
A.6. Power Guidelines x
A.6.1. Primary Mode—As a Standalone Evaluation Board A.6.2. Optional Mode—As a PCIe* Add-in Card in PCIe* Host System
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.3.1. PCI Express* ( PCIe* ) Interface

For PCIe* applications, the power for the Agilex™ 3 FPGA/FPGA and SoC C-Series development board must be sourced by an external USB-PD Type-C power adapter as the board is not designed to receive power from the PCIe* host system.

The board is designed to fit entirely into a PCIe* host system with a x1 PCI Express* slot that can accommodate a full height, 1/2 length form factor add-in card when the optional Altera PCIe* 3.0 x1 gold finger daughter board is installed. The supported data rate for this application is 8 Gbps ( PCIe* 3.0) using the Agilex™ 3 FPGA's PCI Express* hard IP block, saving logic resources for the user logic application.

Table 20.   PCI Express* ( PCIe* ) Pin Assignments with Gold Finger Daughter Board
Gold Finger Pin Number Schematic Signal Name FPGA Pin Number I/O Standard Description
A1 PRSNT1_N — — Card present
A11 RPI_PCIE_X1_RST_B AG26 3.3 V LVCMOS PCIe* reset
A13 RPI_PCIE_REFCLK_P To Si5332 clock generator (U23) HCSL Host PCIe* clock
A14 RPI_PCIE_REFCLK_N To Si5332 clock generator (U23) HCSL Host PCIe* clock
A16 RPI_PCIE_X1_PETP P30 True Differential PCIe* receive lane 0
A17 RPI_PCIE_X1_PETN P29 True Differential PCIe* receive lane 0
B5 FRU_ID_EEPROM_SCL

FRUID EEPROM

(U1 on Altera PCIe* 3.0 x1 gold finger board)

 3.3 V SMB clock
B6 FRU_ID_EEPROM_SDA

FRUID EEPROM

(U1 on Altera PCIe* 3.0 x1 gold finger board)

 3.3 V SMB data
B11 EDGE_PCIE_X1_WAKE AH27 3.3 V PCIe* wake
B12 RPI_PCIE_X1_CLKREQ_N AK19 3.3 V PCIe* Clock request
B14 RPI_PCIE_X1_PERP K30 True Differential PCIe* transmit lane 0
B15 RPI_PCIE_X1_PERP K29 True Differential PCIe* transmit lane 0
B17 PRSNT1_N — — Card present
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