Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide

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ID 851698
Date 9/02/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Ashling* RiscFree* Integrated Development Environment (IDE) 2.3.4. Installing the USB-Blaster III Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Board 3.3. Modes of Operations 3.4. Performing Board Restore
3.4. Performing Board Restore x
3.4.1. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA C-Series Development Kit 3.4.2. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit 3.4.3. Restoring SD Card with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. BTS Functionalities
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Setting Up the Quartus® Prime Software for BTS Operation 4.1.2. Running the BTS GUI
4.2. BTS Functionalities x
4.2.1. The Agilex™ 3 FPGA Functionality 4.2.2. Other Functionalities
4.2.1. The Agilex™ 3 FPGA Functionality x
4.2.1.1. The Configure Menu 4.2.1.2. The GPIO Tab 4.2.1.3. The Memory Tab 4.2.1.4. The Transceiver Tab
4.2.1.2. The GPIO Tab x
4.2.1.2.1. The LED Tab 4.2.1.2.2. The Push Button Tab 4.2.1.2.3. The I2C Bus Tab
4.2.1.3. The Memory Tab x
4.2.1.3.1. The Fabric COMP Tab 4.2.1.3.2. The HPS/Fabric COMP Tab
4.2.1.4. The Transceiver Tab x
4.2.1.4.1. The DP Tab
4.2.2. Other Functionalities x
4.2.2.1. The Bottom Information Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview and Components A.2. Input and Output Components A.3. Components and Interfaces A.4. Clock Circuits A.5. System Power A.6. Power Guidelines A.7. Power Distribution System A.8. Expansion Boards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
A.2. Input and Output Components x
A.2.1. Push Buttons A.2.2. Switches A.2.3. LEDs
A.3. Components and Interfaces x
A.3.1. PCI Express* ( PCIe* ) Interface A.3.2. DisplayPort Interface A.3.3. MIPI Interface A.3.4. LPDDR4 Interfaces A.3.5. Raspberry Pi* , Pmod, and PCIe* x1 Interfaces A.3.6. HPS I/O48 Interface A.3.7. I2C
A.6. Power Guidelines x
A.6.1. Primary Mode—As a Standalone Evaluation Board A.6.2. Optional Mode—As a PCIe* Add-in Card in PCIe* Host System
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

1.2. Feature Summary

  • Agilex™ 3 FPGA/FPGA and SoC C-Series device in 16 mm × 16 mm 896-ball Ball Grid Array (BGA) package
    • Dual-core 64-bit Arm* Cortex* -A55 hard processor (HPS) @ 800 MHz ( Agilex™ 3 FPGA and SoC C-Series device only)
    • Four transceiver TX and RX lanes supporting up to 12.5 Gbps NRZ data rates per lane
    • 135K logic elements (LE)
    • 46.8K adaptive logic modules (ALM)
    • 188 variable precision digital signal processing (DSP) blocks
  • FPGA configuration
    • JTAG header for device programming
    • Built-in USB-Blaster III for device programming
    • Active serial (AS) x4 configuration mode support
    • 512 Mb flash for AS x4
  • Clocking
    • Onboard clock generator
  • Transceiver interfaces
    • PCI Express* ( PCIe* ) x1 interface supporting PCIe* 3.0 root-port and end-point applications with an optional Altera PCIe* gold finger daughter board or Raspberry Pi* 5 M.2 HAT board, respectively.
    • DisplayPort v1.4 transmit and receive interfaces at 8.1 Gbps/lane
  • Memory interfaces
    • Two independent 2 GB LPDDR4 x32 at 2,133 Mbps
  • HPS communication ports (only available on the Agilex™ 3 FPGA and SoC C-Series Development Kit version)
    • 10/100/1000 RJ45 Ethernet
    • 2-wire universal asynchronous receiver–transmitter (UART)
    • USB 2.0 Dual Role Port (DRP) supporting both host and devices mode
    • Micro-SD card slot for HPS Boot
  • Video Interfaces
    • Two independent Mobile Industry Processor Interface (MIPI)
    • DisplayPort v1.4 transmitter
    • DisplayPort v1.4 receiver
  • Expansion Interface
    • 40-pin header for interfacing standard Raspberry Pi* 4/5 daughter cards
    • 22-pin flex cable connector for installing Raspberry Pi* 5 M.2 daughter card or optional Altera PCIe* 3.0 x1 gold finger daughter card
  • HPS/user buttons, switches, I/Os, and status LEDs
    • HPS dedicated general-purpose push button
    • HPS dedicated Cold Reset push button
    • Two user general-purpose push buttons, one can be dedicated for FPGA reset
    • Four general-purpose user DIP switches
    • Four general-purpose user I/Os connected to 0.1 mm headers
    • Two HPS dedicated green LEDs
    • Two dedicated USER green LEDs
    • One tri-color (red/green/blue) for USB-Blaster III cable status LED
    • FPGA configuration done green LED
    • Ethernet Link (green) and Activity (yellow) status LEDs
  • Heatsink and fan
    • Active 5 V fan-cooled heatsink assembly
  • Power
    • USB-PD board power status LED (Green/Red)
    • On/off slide power switch
  • Mechanical
    • 3.8" × 6.6" board size
    • Optional PCIe* gold finger daughter card expansion for conversion into PCIe* full height, half-length add-in card
  • Operating environment
    • 0°C–35°C
Level Two Title