Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide

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ID 851698
Date 9/02/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Ashling* RiscFree* Integrated Development Environment (IDE) 2.3.4. Installing the USB-Blaster III Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Board 3.3. Modes of Operations 3.4. Performing Board Restore
3.4. Performing Board Restore x
3.4.1. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA C-Series Development Kit 3.4.2. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit 3.4.3. Restoring SD Card with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. BTS Functionalities
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Setting Up the Quartus® Prime Software for BTS Operation 4.1.2. Running the BTS GUI
4.2. BTS Functionalities x
4.2.1. The Agilex™ 3 FPGA Functionality 4.2.2. Other Functionalities
4.2.1. The Agilex™ 3 FPGA Functionality x
4.2.1.1. The Configure Menu 4.2.1.2. The GPIO Tab 4.2.1.3. The Memory Tab 4.2.1.4. The Transceiver Tab
4.2.1.2. The GPIO Tab x
4.2.1.2.1. The LED Tab 4.2.1.2.2. The Push Button Tab 4.2.1.2.3. The I2C Bus Tab
4.2.1.3. The Memory Tab x
4.2.1.3.1. The Fabric COMP Tab 4.2.1.3.2. The HPS/Fabric COMP Tab
4.2.1.4. The Transceiver Tab x
4.2.1.4.1. The DP Tab
4.2.2. Other Functionalities x
4.2.2.1. The Bottom Information Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview and Components A.2. Input and Output Components A.3. Components and Interfaces A.4. Clock Circuits A.5. System Power A.6. Power Guidelines A.7. Power Distribution System A.8. Expansion Boards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
A.2. Input and Output Components x
A.2.1. Push Buttons A.2.2. Switches A.2.3. LEDs
A.3. Components and Interfaces x
A.3.1. PCI Express* ( PCIe* ) Interface A.3.2. DisplayPort Interface A.3.3. MIPI Interface A.3.4. LPDDR4 Interfaces A.3.5. Raspberry Pi* , Pmod, and PCIe* x1 Interfaces A.3.6. HPS I/O48 Interface A.3.7. I2C
A.6. Power Guidelines x
A.6.1. Primary Mode—As a Standalone Evaluation Board A.6.2. Optional Mode—As a PCIe* Add-in Card in PCIe* Host System
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.1.2. Board Components

Table 7.  Featured Devices
Board Reference Type Description
U13 FPGA

Agilex™ 3 FPGA C-Series, A3CY135BM16AE6S or Agilex™ 3 FPGA and SoC C-Series, A3CW135BM16AE6S

  • 135K logic elements (LE)
  • 46.8K adaptive logic elements (ALM)
  • 13,272 M20K blocks
  • 45,640 MLABs
  • 188 DSP blocks
  • 212 GPIOs
Table 8.  Configuration, Setup, and Status Elements
Board Reference Type Description
J8 USB-PD compliant power input

USB Type-C input for connecting a USB-PD compliant power adapter capable of providing 27 W (min) for powering the Agilex™ 3 FPGA/FPGA and SoC C-Series Development Kit. For full-load operation, Altera recommends you use a 65 W USB-PD compliant power adapter to cover all workload use cases.
SW3 Power on slide switch This switch turns on and off the board.
D17 Power status LED This bicolor (Red/Green) LED indicates the status of the board power. This LED blinks green when the board is powered up successfully. This LED is off, or blinks red when insufficient power is applied to the board. When the LED blinks red, the USB-PD power contract negotiation was unsuccessful due to an incompatible USB power adapter.
J2 Onboard USB-Blaster III cable
  1. USB Type-C connector to FTDI FT2232H JTAG converter for programming and debugging the FPGA.
  2. USB Type-C connector to FTDI FT2232H UART converter for the HPS 2-wire UART interface.
J4 10-pin JTAG programming header Programming header for connecting an USB-Blaster II/USB-Blaster III programming dongle. When the external dongle is used, the onboard programming feature (FTDI FT2232H) is automatically disabled.
SW1[1:0] USER DIP switches 0 and 1 General-purpose USER DIP switches 0 and 1
SW2[1:0] USER DIP switches 2 and 3 General-purpose USER DIP switches 2 and 3
D7 Dedicated HPS LED 1 One of two green LEDs connected to the FPGA's HPS I/O. The HPS LED1 is connected to HPS_GPIO0_IO11 (U13, pin A26).
D8 Dedicated HPS LED 0 One of two green LEDs connected to the FPGA's HPS I/O. The HPS LED0 is connected to HPS_GPIO0_IO0 (U13, pin B29).
D9 Dedicated USER LED 0 One of two green USER LEDs connected to the FPGA's I/O bank 3A. USER LED 0 is connected to U13 pin K1.
D10 Dedicated USER LED 1 One of two green USER LEDs connected to the FPGA's I/O bank 3A. USER LED 1 is resistor muxed with the transmit DisplayPort's CONFIG_SENSE control signal. USER LED 1 is configured by default and connected to U13 pin L2.
D11 Configuration Done LED Green LED to indicate successful FPGA configuration. This LED is turned on when the FPGA is successfully configured. This LED is turned off when the FPGA is unconfigured.
U2 Tricolor Status LED for onboard USB-Blaster III cable This tricolor LED (red, green, blue) provides status information for the onboard USB-Blaster III.
S1 HPS COLD RESETn push button Dedicated active low HPS COLD RESETn push button. Pushing and releasing this button generates a 20 ms active low pulse to the HPS_COLD_RESETn input of the FPGA.
S2 General-purpose HPS push button

Dedicated general-purpose tactile push button for the HPS interface.

  • Pushing this button drives the HPS push button input logic low.
  • Releasing this button drives the HPS push button input logic high.
S3 General-purpose USER push button

USER dedicated general-purpose tactile push button (PB1/FPGA_RSTN) connected to HSIO bank 3A, pin M1. This pin can be used as a general-purpose push button or as a FPGA RESET push button for user designs.

  • Pushing this button drives the USER push button PB1/FPGA_RSTN input logic low.
  • Releasing this button drives the USER push button PB1/FPGA_RSTN input logic high.
S4 General-purpose USER push button

USER dedicated general-purpose tactile push button (PB0) connected to HSIO bank 3A, pin L1.

  • Pushing this button drives the USER push button PB0 input logic low.
  • Releasing this button drives the USER push button PB0 input logic high.
J6 General-purpose USER IO[3:0] Four dedicated general-purpose USER IO[3:0] with pull-up resistors on even numbered pins 2, 4, 6, and 8. Odd numbered pins 1, 3, 5, and 7 are connected to the board ground.
J1 Pmod interface 12-pin Digilent Pmod* interface for connecting standard Digilent Pmod I/O Interface boards.
J3 Micron-SD card slot Micro-SD card slot for the HPS interface
J5 USB-C 2.0 interface USB 2.0 DRP (Dual Role Port) Type-C connector for the HPS interface
J10 RJ45 Ethernet interface 10/100/1000 Ethernet for the HPS interface
J12 DisplayPort transmit interface DisplayPort v1.4 transmitter interface connected to the FPGA's transceiver bank 1A, lanes[1:0]. Each lane of this interface is capable of 8.1 Gbps data rates.
J16 DisplayPort receive interface DisplayPort v1.4 receiver interface connected to the FPGA's transceiver bank 1A, lanes[1:0]. Each lane of this interface is capable of 8.1 Gbps data rates.
SW4[1:4] DIP Switches

Board configuration DIP switch SW4.1

This feature is used in conjunction with the optional PCIe* 3.0 x1 gold finger daughter card (End-point), or a Raspberry Pi* 5 M.2 HAT board (Root-port).

  • OFF—Sets the board to function as a PCIe* end-point
  • ON—Sets the board to function as a PCIe* root port

Board configuration DIP switch SW4.2

This feature is used in conjunction with the optional PCIe* 3.0 x1 gold finger daughter card (End-point), or a Raspberry Pi* 5 M.2 HAT board (Root-port).

  • OFF—Enables the -0.5% spread spectrum modulation for the PCIe* clock
  • ON—Disables the -0.5% spread spectrum modulation for the PCIe* clock

Board configuration DIP switch SW4.3

  • OFF—Connects a 100 MHz clock to the HVIO bank 5B, pin AJ27
  • ON—Connects the Raspberry Pi* GPIO26 to HVIO bank 5B, pin AJ27

SW4.4

  • OFF—Sets the FPGA to load the USER Application Image from QSPI flash
  • ON—Sets the FPGA to load the Factory Recover Image from QSPI flash
J17 Voltage selection jumper

Voltage selection jumper for HVIO bank 5A

  • Shunting J17 sets the HVIO bank 5A voltage to 1.8 V
  • Leaving J17 open sets the HVIO bank 5A voltage to 3.3 V
J14 Flex cable connector

Flex cable connector for the FPGA transceiver bank 1A, lane 0. Options:

  • Connect the flex cable provided with the optional PCIe* 3.0 x1 gold finger expansion daughter card to J14 to convert the Agilex™ 3 FPGA/FPGA and SoC C-Series Development Kit into a PCIe* adapter card.
  • Connect the flex cable provided with a Raspberry Pi* 5 M.2 HAT daughter board to J14 to interface Raspberry Pi* 5 daughter cards to the Agilex™ 3 FPGA/FPGA and SoC C-Series Development Kit.
J18 Raspberry Pi* 4/5 HAT interface 40-pin header for mounting a Raspberry Pi* 4/5 HAT daughter board. For Raspberry Pi* 5, you should also connect the flex cable to J14.
J20 MIPI bank 2A connector 22-pin FPC MIPI interface connected to bank 2A
J21 MIPI bank 3A connector 22-pin FPC MIPI interface connected to bank 3A
Table 9.  Featured Devices
Board Reference Type Description
U23 Si5332 I2C programmable clock generator

Default frequencies:

  • Out 0—100 MHz CMOS-3.3V for HVIO bank 5B reference clock
  • Out 1—166.67 MHz LVDS-1.8V for LPDDR4 bank 2A reference clock
  • Out 2—166.25 MHz LVDS-1.8V for LPDDR4 bank 3A reference clock
  • Out 3—250 MHz LVDS-1.8V converted to LVCMOS-1.1V for bank 3A PTP reference clock
  • Out 4—125 MHz CMOS-1.8V converted to LVCMOS-1.1V for bank 2A TOD reference clock
  • Out 5—10 MHz CMOS-1.8V converted to LVCOMS-1.1V for bank 2A PPS reference clock
  • Out 6—150 MHz LVDS-1.8V for MIPI bank 2A reference clock
  • Out 7—150 MHz LVDS-1.8V for MIPI bank 3A reference clock
  • Out 8—150 MHz LVDS-1.8V for DisplayPort bank 1A reference clock
  • Out 9—100 MHz PCIe* end-point reference clock connected to FPGA bank 1A
  • Out 10—Not Used
  • Out 11—100 MHz PCIe* root-port reference clock connected to J14 for the Raspberry Pi* 5 M.2 HAT daughter board
Y5 Si510 clock oscillator 100 MHz CMOS-1.8V configuration clock connected to the SDM
Y1 Si510 clock oscillator 25 MHz CMOS-1.8V HPS clock
Table 10.  Transceiver Interfaces
Board Reference Type Description
J14 PCIe* x1 connected to flex cable connector PCIe* TX/RX x1 interface from FPGA bank 1A, lane 0 connected to a flex cable connector (J14). This PCIe* 3.0 x1 interface can be used for the optional PCIe* x1 gold finger daughter card or Raspberry Pi* 5 daughter card.
J12 DisplayPort transmit connector Two TX channels from FPGA bank 1A, lanes 2 and 3 used for DisplayPort transmit interface
J16 DisplayPort receive connector Two RX channels from FPGA bank 1A, lanes 2 and 3 used for DisplayPort receive interface
Table 11.  Memory Devices
Board Reference Type Description
U5 LPDDR4 DRAM LPDDR4 x32 component on bank 2A for FPGA fabric
U9 LPDDR4 DRAM LPDDR4 x32 component on bank 3A for HPS/FPGA fabric
U51 512 Mbit QSPI flash FPGA AS x4 configuration flash
Table 12.  Communication Ports
Board Reference Type Description
J4 10-pin JTAG header For connecting to an external USB-Blaster II/USB-Blaster III dongle
J2 USB Type-C to JTAG connector For connecting to the onboard USB-Blaster III to a host PC for JTAG programming of the FPGA
Table 13.  Miscellaneous Ports
Board Reference Type Description
J7 FAN header 2-pin 5 V FAN header for the FPGA heatsink/fan
J11 Test header For Altera internal testing only
J13 I2C test header 3.3 V I2C test header connected to the HPS IO48 interface
Table 14.  HPS Components and Ports
Board Reference Type Description
J5 USB-C 2.0 Dual Role Port (DRP) USB Type-C connector for USB2.0 interface connected to the HPS IO48 interface
J10 10/100/1000 Ethernet Triple-Speed Ethernet connected to the HPS IO48 interface. This interface supports USB Dual Role Port (DRP).
J2 UART 2-wire UART connected to the HPS IO48 interface
J13 I2C test header 3.3 V I2C test header connected to the HPS IO48 interface
J3 Micro-SD card slot Micro-SD card slot connected to the HPS IO48 interface
J9 Mictor test connector For Altera testing only. This feature is depopulated by default on the board.
J11 I3C test header For Altera testing only. This feature is depopulated by default on the board.
D8 HPS LED0 HPS dedicated LED connected to the HPS IO48 interface
D7 HPS LED1 HPS dedicated LED connected to the HPS IO48 interface
Y1 HPS clock 25 MHz oscillator for the HPS interface
S2 HPS push button HPS dedicated push button connected to the HPS IO48 Interface
Table 15.  Expansion Ports
Board Reference Type Description
J1 Pmod Expansion interface for optional Digilent Pmod* boards connected to HVIO bank 5A.
J18 Raspberry Pi* Expansion interface for optional Raspberry Pi* 4/5 HAT boards connected to HVIO banks 5A and 5B. Raspberry Pi* 4 HAT boards only use the J18 expansion port. Raspberry Pi* 5 HAT boards use J18 and J14 expansion ports.
J14 Flex cable Expansion interface for optional PCIe* 3.0 x1 gold finger daughter board and Raspberry Pi* 5 HAT boards. Raspberry Pi* 4 HAT boards only use the J18 expansion port. Raspberry Pi* 5 HAT boards use J18 and J14 expansion ports.
Table 16.  Power Supplies
Board Reference Type Description
J8 USB-PD Type-C power input Input power range: 9 V @ 3 A to 20 V @ 3.25 A
U10 Texas Instruments TPS25730 USB-PD sink controller
U12 Texas Instruments LM73100 Inrush, reverse polarity, and overvoltage protection controller
U37 Monolithic Power Systems MPQ4731 5 V DC-DC buck regulator
U27 Monolithic Power Systems MPQ4731 3.3 V DC-DC buck regulator
U36 Monolithic Power Systems MPQ2287 0.78 V DC-DC buck regulator for FPGA power
U24 Monolithic Power Systems MPQ4324 1.0 V DC-DC buck regulator for FPGA power
U16 Monolithic Power Systems MPQ4324 1.8 V DC-DC buck regulator for FPGA power
U26 Monolithic Power Systems MPQ4324 1.2 V DC-DC buck regulator for FPGA power
U215 Monolithic Power Systems MPQ4371 1.1 V DC-DC buck regulator for FPGA power
U46 Texas Instruments TPS22917 1.8 V load switch for LPDDR4 memory
U32 Texas Instruments TPS22917 3.3 V load switch for FPGA HVIO bank 5B
U30 Texas Instruments TPS22917 3.3 V load switch for FPGA HVIO bank 5A
U35 Texas Instruments TPS22917 1.8 V load switch for FPGA HVIO bank 5A
U31 Monolithic Power Systems MP5036 5.0 V load switch for Raspberry Pi* header
U39 Texas Instruments TPS22917 3.3 V load switch for Micro-SD card slot
U22 Texas Instruments TLV75518 1.8 V LDO for clock power (optional, DNI by default)
U28 Texas Instruments TLV75533 3.3 V LDO for clock power (optional, DNI by default)
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