Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide

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ID 851698
Date 9/02/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Ashling* RiscFree* Integrated Development Environment (IDE) 2.3.4. Installing the USB-Blaster III Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Board 3.3. Modes of Operations 3.4. Performing Board Restore
3.4. Performing Board Restore x
3.4.1. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA C-Series Development Kit 3.4.2. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit 3.4.3. Restoring SD Card with Default Factory Image on Agilex™ 3 FPGA and SoC C-Series Development Kit
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. BTS Functionalities
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Setting Up the Quartus® Prime Software for BTS Operation 4.1.2. Running the BTS GUI
4.2. BTS Functionalities x
4.2.1. The Agilex™ 3 FPGA Functionality 4.2.2. Other Functionalities
4.2.1. The Agilex™ 3 FPGA Functionality x
4.2.1.1. The Configure Menu 4.2.1.2. The GPIO Tab 4.2.1.3. The Memory Tab 4.2.1.4. The Transceiver Tab
4.2.1.2. The GPIO Tab x
4.2.1.2.1. The LED Tab 4.2.1.2.2. The Push Button Tab 4.2.1.2.3. The I2C Bus Tab
4.2.1.3. The Memory Tab x
4.2.1.3.1. The Fabric COMP Tab 4.2.1.3.2. The HPS/Fabric COMP Tab
4.2.1.4. The Transceiver Tab x
4.2.1.4.1. The DP Tab
4.2.2. Other Functionalities x
4.2.2.1. The Bottom Information Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview and Components A.2. Input and Output Components A.3. Components and Interfaces A.4. Clock Circuits A.5. System Power A.6. Power Guidelines A.7. Power Distribution System A.8. Expansion Boards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
A.2. Input and Output Components x
A.2.1. Push Buttons A.2.2. Switches A.2.3. LEDs
A.3. Components and Interfaces x
A.3.1. PCI Express* ( PCIe* ) Interface A.3.2. DisplayPort Interface A.3.3. MIPI Interface A.3.4. LPDDR4 Interfaces A.3.5. Raspberry Pi* , Pmod, and PCIe* x1 Interfaces A.3.6. HPS I/O48 Interface A.3.7. I2C
A.6. Power Guidelines x
A.6.1. Primary Mode—As a Standalone Evaluation Board A.6.2. Optional Mode—As a PCIe* Add-in Card in PCIe* Host System
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 3 FPGA and SoC C-Series Development Kits User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.3.7. I2C

An I2C bus is used to connect various devices and interfaces to the Agilex™ 3 FPGA.

For the Agilex™ 3 FPGA and SoC C-Series Development Kit version, the I2C chain is connected to the HPS IO48 interface so that the HPS is the I2C master. For the Agilex™ 3 FPGA C-Series Development Kit version, the I2C chain connects to HVIO bank 5A. In this case, you can implement an I2C master in the FPGA fabric to communicate with the connected I2C devices on the chain.

Figure 29. I2C Block Diagram
Table 29.  FPGA I2C Signals
Schematic Signal Name FPGA Pin Number I/O Standard Description
HPS_I2C_SCL F23 1.8 V open drain

HPS I2C clock connected to Si5332 programmable clock generator, DisplayPort TX redriver, DisplayPort RX redriver, USB-PD input power sink controller, FPGA VCC core regulator, 8-bit I/O expander, and I2C 3-pin test header.

This signal is only applicable for the Agilex™ 3 FPGA and SoC C-Series Development Kit.
HPS_I2C_SDA B28 1.8 V open drain

HPS I2C data connected to Si5332 programmable clock generator, DisplayPort TX redriver, DisplayPort RX redriver, USB-PD input power sink controller, FPGA VCC core regulator, 8-bit I/O expander, and I2C 3-pin test header.

This signal is only applicable for the Agilex™ 3 FPGA and SoC C-Series Development Kit.
MIPI_CONN_1_SCL AH28 3.3 V open drain HVIO bank 5B I2C clock connected to FPC MIPI 2A connector
MIPI_CONN_1_SDA AK20 3.3 V open drain HVIO bank 5B I2C data connected to FPC MIPI 2A connector
MIPI_CONN_2_SCL AK21 3.3 V open drain HVIO bank 5B I2C clock connected to FPC MIPI 3A connector
MIPI_CONN_2_SDA AK27 3.3 V open drain HVIO bank 5B I2C data connected to FPC MIPI 3A connector
RPI_ID_SC AF21 3.3 V open drain

HVIO bank 5A I2C clock connected to Raspberry Pi* 40-pin header/Pmod connector

This signal is only applicable for the Agilex™ 3 FPGA C-Series Development Kit.
RPI_ID_SD AF19 3.3V open drain

HVIO bank 5A I2C clock connected to Raspberry Pi* 40-pin header/Pmod connector

This signal is only applicable for the Agilex™ 3 FPGA C-Series Development Kit.
Table 30.  I2C Address
Device Reference I2C Address Description
TPS25730DREFR U10 0x21 Texas Instruments USB-PD input power sink controller
MPQ2287GLE U36 0x03 MPS voltage regulator for FPGA core power
SI5332LD16712-GM3 U23 0x6A Skyworks I2C programmable clock generator
PCA9574PW U45 0x20 NXP I2C to 8-bit I/O expander
PI2DPX2063FLAEX U264 0x53 Diodes Inc DisplayPort ReDriver* used for TX
PI2DPX2063FLAEX U265 0x52 Diodes Inc DisplayPort ReDriver* used for RX
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