GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

ID 848344
Date 8/04/2025
Public
Document Table of Contents

2.6.3.2. System PLL Clock for FPGA Core

If the system PLL is not used by the GTS transceiver bank, it can be used by the FPGA core. In this case, up to two clock outputs (C0 and C1) can be generated by the system PLL and fed to the FPGA core.