GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

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ID 848344
Date 8/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS Transceiver Overview 2. GTS Transceiver Architecture 3. Implementing the GTS PMA/FEC Direct PHY IP 4. Implementing the GTS System PLL Clocks IP 5. Implementing the GTS Reset Sequencer IP 6. GTS PMA/FEC Direct PHY IP Example Design 7. Design Assistance Tools 8. Debugging GTS Transceiver Links with Transceiver Toolkit 9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs
1. GTS Transceiver Overview x
1.1. GTS Transceiver Design Flow
2. GTS Transceiver Architecture x
2.1. Building Blocks 2.2. Channel Placement Rules and Design Requirements 2.3. PMA Architecture 2.4. PCS Architecture 2.5. Forward Error Correction (FEC) Architecture 2.6. Clock Architecture 2.7. Bonding and Deskew
2.1. Building Blocks x
2.1.1. PMA 2.1.2. FEC 2.1.3. PCS 2.1.4. Ethernet MAC 2.1.5. PCI Express* Hard IP 2.1.6. PLL and Clock Networks 2.1.7. Avalon® Memory-Mapped Interface
2.1.1. PMA x
2.1.1.1. Protocol Support Using PMA Direct Mode
2.1.1.1. Protocol Support Using PMA Direct Mode x
2.1.1.1.1. SDI 2.1.1.1.2. HDMI 2.1.1.1.3. OTN
2.2. Channel Placement Rules and Design Requirements x
2.2.1. Hard IP Rules 2.2.2. Use Scenario Rules 2.2.3. Unused PMA Rules 2.2.4. General Design Requirement
2.2.3. Unused PMA Rules x
2.2.3.1. Unused PMA Not Planned for Use in the Future 2.2.3.2. Unused PMA Planned for Use in the Future
2.3. PMA Architecture x
2.3.1. Transmitter PMA Architecture 2.3.2. Receiver PMA Architecture 2.3.3. PMA Loopback Modes
2.3.1. Transmitter PMA Architecture x
2.3.1.1. Transmitter Buffer 2.3.1.2. Serializer 2.3.1.3. Data Pattern Generator and Verifier
2.3.2. Receiver PMA Architecture x
2.3.2.1. Receiver Buffer and Equalizer 2.3.2.2. Deserializer 2.3.2.3. CDR Block 2.3.2.4. RX PMA Tuning 2.3.2.5. RX PMA Adaptation Modes
2.3.2.1. Receiver Buffer and Equalizer x
2.3.2.1.1. Control Unit
2.3.2.5. RX PMA Adaptation Modes x
2.3.2.5.1. RX Auto Adaptation Mode 2.3.2.5.2. RX Manual Adaptation Mode 2.3.2.5.3. RX Native Adaptation Mode
2.5. Forward Error Correction (FEC) Architecture x
2.5.1. FEC Loopback Mode
2.6. Clock Architecture x
2.6.1. Reference Clock Network 2.6.2. Datapath Clock Network 2.6.3. System PLL 2.6.4. Datapath Clock Cadences 2.6.5. Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank
2.6.1. Reference Clock Network x
2.6.1.1. PMA Primary PLL Configuration
2.6.3. System PLL x
2.6.3.1. I/O PLL in HVIO Bank as System PLL 2.6.3.2. System PLL Clock for FPGA Core 2.6.3.3. System PLL with HVIO Reference Clock
2.7. Bonding and Deskew x
2.7.1. Bonding Architecture 2.7.2. TX Deskew Function
3. Implementing the GTS PMA/FEC Direct PHY IP x
3.1. IP Overview 3.2. Designing with the GTS PMA/FEC Direct PHY IP 3.3. Configuring the GTS PMA/FEC Direct PHY IP 3.4. Dynamically Reconfigurable PHY 3.5. Signal and Port Reference 3.6. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath 3.7. Clocking 3.8. Custom Cadence Generation Ports and Logic 3.9. Asserting Reset 3.10. Bonding Implementation 3.11. Configuration Register 3.12. Configuring the GTS PMA/FEC Direct PHY IP for Hardware Testing 3.13. Configurable Quartus® Prime Software Settings 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. PCS Direct Supported Modes 3.1.4. Unsupported PMA/FEC/PCS Modes
3.3. Configuring the GTS PMA/FEC Direct PHY IP x
3.3.1. Preset IP Parameter Settings 3.3.2. Mode and Common Datapath Options 3.3.3. TX Datapath Options 3.3.4. RX Datapath Options 3.3.5. PMA Configuration Rules for Specific Protocol Mode Implementations 3.3.6. FEC Options 3.3.7. PCS Options 3.3.8. Avalon® Memory-Mapped Interface Options 3.3.9. Register Map IP-XACT Support 3.3.10. Analog Parameter Options
3.3.2. Mode and Common Datapath Options x
3.3.2.1. Reconfigurable PHY Settings
3.3.3. TX Datapath Options x
3.3.3.1. TX PMA Interface Parameters
3.3.4. RX Datapath Options x
3.3.4.1. RX PMA Interface Parameters
3.3.5. PMA Configuration Rules for Specific Protocol Mode Implementations x
3.3.5.1. PMA Configuration Rules for SDI Mode 3.3.5.2. PMA Configuration Rules for HDMI Mode 3.3.5.3. PMA Configuration Rules for OTN Mode
3.4. Dynamically Reconfigurable PHY x
3.4.1. Clock Generation and Constraints for Multiple Profiles Design
3.5. Signal and Port Reference x
3.5.1. TX and RX Parallel and Serial Interface Signals 3.5.2. TX and RX Reference Clock and Clock Output Interface Signals 3.5.3. Reset Signals 3.5.4. FEC Signals 3.5.5. Custom Cadence Control and Status Signals 3.5.6. RX PMA Status Signals 3.5.7. TX and RX PMA and Core Interface FIFO Signals 3.5.8. Avalon Memory-Mapped Interface Signals
3.7. Clocking x
3.7.1. Clock Ports 3.7.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.7.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.7.4. PMA Fractional Mode 3.7.5. Input Reference Clock Buffer Protection 3.7.6. Guidelines for Obtaining the Real-Time GTS TX PLL Lock Status
3.7.5. Input Reference Clock Buffer Protection x
3.7.5.1. Reference Clock Buffer Register Information 3.7.5.2. Re-enabling the Reference Clock Buffers
3.8. Custom Cadence Generation Ports and Logic x
3.8.1. Implementing PMA Direct Mode with TX Core FIFO in Elastic Configuration 3.8.2. Enabling the i_tx_cadence_slow_clk_locked Port
3.9. Asserting Reset x
3.9.1. Reset Signal Requirements 3.9.2. Power On Reset Requirements 3.9.3. Reset Signals—Block Level 3.9.4. Run-time Reset Sequence—TX 3.9.5. Run-time Reset Sequence—RX 3.9.6. Run-time Reset Sequence—TX + RX 3.9.7. RX Data Loss/CDR Lock Loss (Auto-Recovery) 3.9.8. TX PLL Lock Loss
3.10. Bonding Implementation x
3.10.1. Bonding Placement Requirements 3.10.2. Multilane RX Simplex Implementation
3.11. Configuration Register x
3.11.1. GTS PMA and FEC Direct PHY Soft CSR Register Map 3.11.2. GTS PMA Register Map 3.11.3. Accessing Configuration Registers
3.11.2. GTS PMA Register Map x
3.11.2.1. Logical Avalon® Memory-Mapped Port Indexing
3.11.3. Accessing Configuration Registers x
3.11.3.1. Accessing GTS PMA and FEC Direct PHY Soft CSR Registers 3.11.3.2. Accessing GTS PMA Registers
3.12. Configuring the GTS PMA/FEC Direct PHY IP for Hardware Testing x
3.12.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY IP 3.12.2. Using JTAG to Avalon Master Bridge IP
3.12.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY IP x
3.12.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.12.2. Using JTAG to Avalon Master Bridge IP x
3.12.2.1. RTL Connection Example for JTAG to Avalon Master Bridge IP
3.13. Configurable Quartus® Prime Software Settings x
3.13.1. Configuring the RX Adaptation Mode and PMA Manual Tuning
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.14.1. Direct Register Method 3.14.2. GTS Attribute Access Method
3.14.1. Direct Register Method x
3.14.1.1. Direct Register Method Examples
3.14.2. GTS Attribute Access Method x
3.14.2.1. GTS Attribute Access Method Example 1: Enable or Disable Internal Serial Loopback Mode (RX Auto Adaptation Mode) 3.14.2.2. GTS Attribute Access Method Example 2: Enable or Disable Internal Serial Loopback Mode (RX Manual Adaptation Mode) 3.14.2.3. GTS Attribute Access Method Example 3: Enable or Disable Polarity Inversion of the PMA 3.14.2.4. GTS Attribute Access Method Example 4: Enable PRBS Generator and Checker to Run BER Test
4. Implementing the GTS System PLL Clocks IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for GTS System PLL Clocks IP Usage 4.5. Guidelines to Indicate System PLL Reference Clock is Ready
4.5. Guidelines to Indicate System PLL Reference Clock is Ready x
4.5.1. Example Flow to Indicate System PLL Reference Clock is Ready
5. Implementing the GTS Reset Sequencer IP x
5.1. IP Requirements 5.2. IP Parameters 5.3. IP Port List 5.4. GTS Reset Sequencer IP General Interface 5.5. GTS Reset Sequencer IP Design Flow 5.6. GTS Reset Sequencer IP Use Cases 5.7. Connecting the Reference Clock Buffer Status to the GTS Reset Sequencer IP
5.6. GTS Reset Sequencer IP Use Cases x
5.6.1. Example Use Case 1 5.6.2. Example Use Case 2
6. GTS PMA/FEC Direct PHY IP Example Design x
6.1. Instantiating the GTS PMA/FEC Direct PHY IP 6.2. Generating the GTS PMA/FEC Direct PHY IP Example Design 6.3. GTS PMA/FEC Direct PHY IP Example Design Functional Description 6.4. Simulating the GTS PMA/FEC Direct PHY IP Example Design Testbench 6.5. Compiling the GTS PMA/FEC Direct PHY IP Example Design 6.6. GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design 6.7. Generating the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable Example Design 6.8. GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design Functional Description 6.9. Simulating the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design Testbench 6.10. Compiling the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design
6.2. Generating the GTS PMA/FEC Direct PHY IP Example Design x
6.2.1. Fast Simulation Support 6.2.2. GTS PMA/FEC Direct PHY IP Example Design Directory Structure
6.4. Simulating the GTS PMA/FEC Direct PHY IP Example Design Testbench x
6.4.1. Modifying the Example Design and Performing Simulation
6.7. Generating the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable Example Design x
6.7.1. Fast Simulation Support 6.7.2. GTS PMA/FEC Direct PHY IP Reconfigurable PHY Example Design Directory Structure
7. Design Assistance Tools x
7.1. Clocking and Datapath Tool 7.2. TX Equalizer Tool
8. Debugging GTS Transceiver Links with Transceiver Toolkit x
8.1. GTS Transceiver Toolkit Parameter Settings 8.2. GTS Transceiver Toolkit GUI 8.3. GTS Transceiver Debugging Flow Walkthrough
8.2. GTS Transceiver Toolkit GUI x
8.2.1. Collection View
8.3. GTS Transceiver Debugging Flow Walkthrough x
8.3.1. Modifying the Design to Enable GTS Transceiver Debug Toolkit 8.3.2. Programming the Design into an Altera FPGA 8.3.3. Loading the Design to the Transceiver Toolkit 8.3.4. Creating Transceiver Links 8.3.5. Running BER Tests 8.3.6. Running Eye Viewer Tests 8.3.7. Running Link Optimization Tests
1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY IP
4. Implementing the GTS System PLL Clocks IP
5. Implementing the GTS Reset Sequencer IP
6. GTS PMA/FEC Direct PHY IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

3.3.4.1. RX PMA Interface Parameters

Figure 34. RX PMA Interface Options in Parameter Editor
Table 25.   RX PMA Interface Parameters
Parameter Values Description
RX PMA Interface Parameters
RX PMA interface FIFO mode

Register

Elastic

 Selects the RX PMA Interface FIFO mode. Default value is Elastic. Refer to PMA Direct Mode Support for more information.
Enable rx_pmaif_fifo_empty port On/Off Enables the port that indicates the RX PMA Interface FIFO's empty condition. Default value is Off.
Enable rx_pmaif_fifo_pempty port On/Off Enables the port that indicates the RX PMA Interface FIFO's partially empty condition. Default value is Off.
Enable rx_pmaif_fifo_pfull port On/Off Enables the port that indicates the RX PMA Interface FIFO's partially full condition. Default value is Off.
RX Core Interface Parameters
RX core interface FIFO mode

Phase compensation

Elastic

 Specifies the mode for the RX Core Interface FIFO. Default value is Phase compensation. Elastic mode is only supported for PMA Clocking mode. When you select Elastic mode for the TX core interface FIFO, custom cadence generation logic is enabled by default.
Enable RX double width transfer On/Off Enables double width RX data transfer mode. In this mode, core logic can be clocked with a half rate clock. Default value is On.
Enable rx_fifo_full port On/Off Enables the optional o_rx_fifo_full status output port. This signal indicates when the RX core FIFO has reached the full threshold. This signal is synchronous with o_rx_clkout. Default value is Off.
Enable rx_fifo_empty port On/Off Enables the optional o_rx_fifo_empty status output port. This signal indicates when the RX core FIFO has reached the empty threshold. This signal is synchronous with o_rx_clkout. Default value is Off.
Enable rx_fifo_pfull port On/Off Enables the optional o_rx_fifo_pfull status output port. This signal indicates when the RX core FIFO has reached the specified partially full threshold. Default value is Off.
Enable rx_fifo_pempty port On/Off Enables the optional o_rx_fifo_pempty status output port. This signal indicates when the RX core FIFO has reached the specified partially empty threshold. Default value is Off.
Enable rx_fifo_rd_en port On/Off Enables the optional i_rx_fifo_rd_en control input port. This port is used for Elastic FIFO mode. Asserting this signal enables the read from RX core FIFO. You must enable this read enable when using Elastic FIFO. Default value is Off.
RX Clock Options
Selected rx_clkout clock source

Word Clock

RX User Clock

Sys PLL Clock

 Specifies the o_rx_clkout output port source. Default value is Sys PLL Clock.
Frequency of rx_clkout Output Displays the frequency of o_rx_clkout in MHz based on o_rx_clkout source selection.
Enable rx_clkout2 port On/Off Enables the optional o_rx_clkout2 output clock. Default value is Off.
Selected rx_clkout2 clock source

Word Clock

RX User Clock

Sys PLL Clock

 Specifies the o_rx_clkout output port source. Default value is Word Clock.
rx_clkout2 clock div by 1, 2, 4 Selects the RX clock out 2 divider setting that divides out the o_rx_clkout2 output port source. Default value is 1.
Frequency of rx_clkout2 Output Displays the frequency of o_rx_clkout2 in MHz based on o_rx_clkout2 source selection and o_rx_clkout2 clock divide by factor.
RX User Clock Settings
RX user clock div by 12-139.5 Division factor from Fvco of RX CDR to RX user clock. Values from 12 to 139.5 are acceptable in 0.5 increments. Default value is 100.
RX user clock Frequency Output Displays the frequency of RX user clock in MHz based on RX user clock divide by factor.
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