GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

ID 848344
Date 8/04/2025
Public
Document Table of Contents

3.9.4. Run-time Reset Sequence—TX

Figure 47. Run-time Reset Sequence—TX

The figure above illustrates the following run-time TX reset sequence:23

  1. Assert i_tx_reset.
  2. o_tx_ready deasserts, indicating that the TX datapath is no longer operational.
  3. o_tx_pll_locked deasserts.
  4. o_tx_reset_ack asserts, indicating that the TX datapath is fully in reset. o_tx_reset_ack stays asserted until i_tx_reset deasserts.
  5. You then deassert i_tx_reset to bring TX out of reset.
  6. o_tx_pll_locked asserts as the TX PLL locks to the reference clock.
  7. o_tx_ready asserts.
Note: o_tx_pll_locked may have different behavior in simulation.
Note: This flow is also applicable in RS-FEC mode. In RS-FEC mode, the alignment marker operation is done internally after o_tx_pll_locked is asserted.
23 All timing diagrams show relative signal behavior and the waves do not show actual durations in time.