GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

ID 848344
Date 8/04/2025
Public
Document Table of Contents

3.5.3. Reset Signals

Table 37.  Reset Signals
Signal Name Clocks Domains Direction Description
i_tx_reset asynchronous input TX reset input for TX PMA and TX datapath. Must be kept asserted until o_tx_reset_ack is asserted.
i_rx_reset asynchronous input RX reset input for RX PMA and RX datapath. Must be kept asserted until o_rx_reset_ack is asserted.
o_tx_reset_ack asynchronous output TX fully in reset indicator. o_tx_reset_ack indicates that the PMA is in reset. It asserts after the assertion of i_tx_reset, and deasserts after the deassertion of i_tx_reset.
o_rx_reset_ack asynchronous output RX fully in reset indicator. o_rx_reset_ack indicates that the PMA is in reset. It asserts after the assertion of i_rx_reset and deasserts after the deassertion of i_rx_reset.
o_tx_ready asynchronous output Status port to indicate when TX PMA and TX datapath are reset successfully and ready for data transfer.
o_rx_ready asynchronous output

Status port to indicate when RX PMA and RX datapath are reset successfully and ready for data transfer.

o_src_rs_req[N-1:0] asynchronous output Request signal from Soft Reset Controller (SRC) to GTS Reset Sequencer IP for reset operation. Asserts when there is a request to toggle reset.
i_src_rs_grant[N-1:0] asynchronous input Grant signal from GTS Reset Sequencer IP to SRC. Asserts when the reset request is granted by Reset Sequencer IP.
i_pma_cu_clk clock input

PMA Control Unit clock source. This clock port must be connected from the GTS Reset Sequencer IP.

o_refclk_bus_out asynchronous output Reference clock failed status signal from the GTS PMA/FEC Direct PHY IP to GTS Reset Sequencer IP. Refer to Connecting the Reference Clock Buffer Status to the GTS Reset Sequencer IP for more details about connecting this signal.