GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

ID 848344
Date 8/04/2025
Public
Document Table of Contents

3.7.5.2. Re-enabling the Reference Clock Buffers

Re-enabling the clock buffers is done through the Avalon® memory-mapped interface that you use to access the GTS PMA registers. You must select an IP to use the Avalon® memory-mapped interface. If there are multiple IPs in your design, only one IP (non- PCIe* ) needs to be selected.

All the required read and write operations are performed through the selected IP’s Avalon® memory-mapped interface.

The steps to re-enable the clock buffers are as follows:
  1. There are 2 ways to determine if a reference clock buffer has been turned off.
    1. Poll the status register at address (0xA6038[15:8]) that provides the live reference clock buffer status. A 1 in any of these bits indicates a particular reference clock buffer is turned off.
      • The minimum polling interval for this register is 200 μs for every enabled reference clock buffer on the same side of the device. For example, if both the reference clocks are used, then the minimum polling interval is 400 μs ms (2 x 200 μs).
    2. Alternatively, there is an output signal from the GTS Reset Sequencer IP called o_shoreline_refclk_fail_stat, which is an interrupt that is asserted when any reference clock buffer has been turned off. Refer to Connecting the Reference Clock Buffer Status to the GTS Reset Sequencer IP for more details about connecting this signal.
  2. Once you detect that a reference clock buffer is turned off, you must reset the affected lanes (for example, if both TX and RX share the same reference clock, then both must be reset).
  3. You must then bring the reference clock back up.
  4. To re-enable the clock buffer you must write to the corresponding bit of register 0xA6038[23:16]. Use a byte access to perform this write operation.
  5. Check the acknowledgment in status register 0xA6038[15:8] to confirm that clock buffer has turned on. Poll every 100 us until the bit corresponding bit is cleared. A 0 in the register bit indicates that the buffer has been turned back on.
  6. Release the lane resets.
  7. Repeat all the steps from step 1 if the input reference clock goes down again.