GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs
ID
848344
Date
8/04/2025
Public
1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY IP
4. Implementing the GTS System PLL Clocks IP
5. Implementing the GTS Reset Sequencer IP
6. GTS PMA/FEC Direct PHY IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY IP
3.3. Configuring the GTS PMA/FEC Direct PHY IP
3.4. Dynamically Reconfigurable PHY
3.5. Signal and Port Reference
3.6. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath
3.7. Clocking
3.8. Custom Cadence Generation Ports and Logic
3.9. Asserting Reset
3.10. Bonding Implementation
3.11. Configuration Register
3.12. Configuring the GTS PMA/FEC Direct PHY IP for Hardware Testing
3.13. Configurable Quartus® Prime Software Settings
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.3.1. Preset IP Parameter Settings
3.3.2. Mode and Common Datapath Options
3.3.3. TX Datapath Options
3.3.4. RX Datapath Options
3.3.5. PMA Configuration Rules for Specific Protocol Mode Implementations
3.3.6. FEC Options
3.3.7. PCS Options
3.3.8. Avalon® Memory-Mapped Interface Options
3.3.9. Register Map IP-XACT Support
3.3.10. Analog Parameter Options
3.5.1. TX and RX Parallel and Serial Interface Signals
3.5.2. TX and RX Reference Clock and Clock Output Interface Signals
3.5.3. Reset Signals
3.5.4. FEC Signals
3.5.5. Custom Cadence Control and Status Signals
3.5.6. RX PMA Status Signals
3.5.7. TX and RX PMA and Core Interface FIFO Signals
3.5.8. Avalon Memory-Mapped Interface Signals
3.7.1. Clock Ports
3.7.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source
3.7.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2
3.7.4. PMA Fractional Mode
3.7.5. Input Reference Clock Buffer Protection
3.7.6. Guidelines for Obtaining the Real-Time GTS TX PLL Lock Status
3.14.2.1. GTS Attribute Access Method Example 1: Enable or Disable Internal Serial Loopback Mode (RX Auto Adaptation Mode)
3.14.2.2. GTS Attribute Access Method Example 2: Enable or Disable Internal Serial Loopback Mode (RX Manual Adaptation Mode)
3.14.2.3. GTS Attribute Access Method Example 3: Enable or Disable Polarity Inversion of the PMA
3.14.2.4. GTS Attribute Access Method Example 4: Enable PRBS Generator and Checker to Run BER Test
6.1. Instantiating the GTS PMA/FEC Direct PHY IP
6.2. Generating the GTS PMA/FEC Direct PHY IP Example Design
6.3. GTS PMA/FEC Direct PHY IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY IP Example Design
6.6. GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design
6.7. Generating the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable Example Design
6.8. GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design Functional Description
6.9. Simulating the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design Testbench
6.10. Compiling the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design
8.3.1. Modifying the Design to Enable GTS Transceiver Debug Toolkit
8.3.2. Programming the Design into an Altera FPGA
8.3.3. Loading the Design to the Transceiver Toolkit
8.3.4. Creating Transceiver Links
8.3.5. Running BER Tests
8.3.6. Running Eye Viewer Tests
8.3.7. Running Link Optimization Tests
3.7.5.2. Re-enabling the Reference Clock Buffers
Re-enabling the clock buffers is done through the Avalon® memory-mapped interface that you use to access the GTS PMA registers. You must select an IP to use the Avalon® memory-mapped interface. If there are multiple IPs in your design, only one IP (non- PCIe* ) needs to be selected.
All the required read and write operations are performed through the selected IP’s Avalon® memory-mapped interface.
The steps to re-enable the clock buffers are as follows:
- There are 2 ways to determine if a reference clock buffer has been turned off.
- Poll the status register at address (0xA6038[15:8]) that provides the live reference clock buffer status. A 1 in any of these bits indicates a particular reference clock buffer is turned off.
- The minimum polling interval for this register is 200 μs for every enabled reference clock buffer on the same side of the device. For example, if both the reference clocks are used, then the minimum polling interval is 400 μs ms (2 x 200 μs).
- Alternatively, there is an output signal from the GTS Reset Sequencer IP called o_shoreline_refclk_fail_stat, which is an interrupt that is asserted when any reference clock buffer has been turned off. Refer to Connecting the Reference Clock Buffer Status to the GTS Reset Sequencer IP for more details about connecting this signal.
- Poll the status register at address (0xA6038[15:8]) that provides the live reference clock buffer status. A 1 in any of these bits indicates a particular reference clock buffer is turned off.
- Once you detect that a reference clock buffer is turned off, you must reset the affected lanes (for example, if both TX and RX share the same reference clock, then both must be reset).
- You must then bring the reference clock back up.
- To re-enable the clock buffer you must write to the corresponding bit of register 0xA6038[23:16]. Use a byte access to perform this write operation.
- Check the acknowledgment in status register 0xA6038[15:8] to confirm that clock buffer has turned on. Poll every 100 us until the bit corresponding bit is cleared. A 0 in the register bit indicates that the buffer has been turned back on.
- Release the lane resets.
- Repeat all the steps from step 1 if the input reference clock goes down again.