GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

ID 848344
Date 8/04/2025
Public
Document Table of Contents

5.1. IP Requirements

The GTS Reset Sequencer IP must be instantiated for device that uses transceivers. Refer to the Transceiver Architecture chapter for more information.

The following table shows the logic usage in the FPGA fabric of the GTS Reset Sequencer IP.
Table 79.  Logic Usage of the GTS Reset Sequencer IP (For Agilex® 3 C-Series Devices)
Device Family ALM30 ALUT Logic Register M20K
Agilex® 3 C-Series 52 79 73 0
30 Logic utilization is lower for fewer channel applications.