GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

ID 848344
Date 8/04/2025
Public
Document Table of Contents

5.2. IP Parameters

The table below lists the IP parameters for the GTS Reset Sequencer IP.
Figure 67. GTS Reset Sequencer IP Parameter Editor
Table 80.  GTS Reset Sequencer IP Parameters
Parameter Name Default Range Description
Enable PCIE and/or HPS USB3.1 only design Off

On/Off

Enable or disable the Enable PCIE and/or HPS USB3.1 only design setting per GTS Reset Sequencer IP.

Enable – Only the pma_cu_clk port is available from the GTS Reset Sequencer IP.

Disable – All ports are available from the GTS Reset Sequencer IP.

Note: Enable this feature if you are using PCIe* only or HPS USB3.1 only.
Number of Reset Sequencer Lane(s) 1 1 - 4 Number of Reset Sequencer lanes to be connected to the GTS Reset Sequencer IP.
Note: The Number of Reset Sequencer Lane(s) parameter must be set to the exact number of reset sequencer request or grant signals used and you cannot leave them unconnected. The Number of Reset Sequencer Lane(s) parameter does not include PCIe* and HPS USB3.1 channels.
Number of Bank(s) 1 1 Number of banks per GTS Reset Sequencer IP.
Note: The Number of Bank(s) parameter cannot be left unconnected.