GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

ID 848344
Date 8/04/2025
Public
Document Table of Contents

3.7.6. Guidelines for Obtaining the Real-Time GTS TX PLL Lock Status

To get the real-time status of the TX PLL lock status, you must perform read operations from certain status registers using the Avalon® memory-mapped interface. The register locations are shown in the following table. They are listed for all the three PLLs that make up the TXPLL of a channel. A value of 1’b1 indicates that the TX PLL is locked to the reference clock.
Table 58.  GTS TX PLL Avalon Memory-Mapped Address
GTS Channel PLL Address and Bit
0 Fast 0x09428C[2]
0 Medium 0x09418C[2]
0 Slow 0x09408C[2]
1 Fast 0x19428C[2]
1 Medium 0x19418C[2]
1 Slow 0x19408C[2]
2 Fast 0x29428C[2]
2 Medium 0x29418C[2]
2 Slow 0x29408C[2]
3 Fast 0x39428C[2]
3 Medium 0x39418C[2]
3 Slow 0x39408C[2]
To determine the PLL that is being used in your design, you can refer to the System Messages tab of the GTS PMA/FEC Direct PHY IP. The tab lists either the TX_PLL_FAST, TX_PLL_MEDIUM, or TX_PLL_SLOW as the PLL in the design as shown in the following figure.
Figure 44. System Message for TX PLL Settings