GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

ID 848344
Date 8/04/2025
Public
Document Table of Contents

5.5. GTS Reset Sequencer IP Design Flow

The design flow for the GTS Reset Sequencer IP is described below:
  1. Add the GTS Reset Sequencer IP from the IP Catalog into your design as shown in the following figure.
    Figure 69. IP Catalog
  2. Select the total Number of Reset Sequencer Lane(s) that you want to use for the GTS Reset Sequencer IP as shown in the following figure.
    Figure 70. IP Parameters for Lane Selection
  3. Connect o_src_rs_grant and i_src_rs_req to the channels. The o_src_rs_grant and i_src_rs_req must be connected to the same channel so that the reset operation works accordingly. For simplex applications, each simplex PMA occupies one channel; therefore, it needs its own o_src_rs_grant and i_src_rs_req signals.
    Note: For dual simplex mode, you must connect each RX and TX channel to the same o_src_rs_grant and i_src_rs_req signals.
  4. Connect o_pma_cu_clk to i_pma_cu_clk input of the GTS PMA/FEC Direct PHY IP and protocol IPs.
  5. For channels that need to be prioritized for reset sequencing, tie i_src_rs_priority to 1 for that specific channel based on the connection of bits o_src_rs_grant and i_src_rs_req for that channel. For non-priority (normal) reset sequence channels, tie the i_src_rs_priority to 0. For example, the value 4’b0010, sets the priority to lane 2.
Note: You can skip steps 2, 3, and 5, if you set the Enable PCIE and/or HPS USB3.1 only design option to Enable in the IP parameter GUI, since the parameters and ports are unavailable. If you are using Platform Designer, for steps 3 and , you must connect o_src_rs_grant, i_src_rs_req, and o_pma_cu_clk signals using wire-level expressions. Refer Editing Wire-Level Expressions in the Quartus® Prime Pro Edition User Guide: Platform Designer for more details.