GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

ID 848344
Date 8/04/2025
Public
Document Table of Contents

3.4.1. Clock Generation and Constraints for Multiple Profiles Design

Clocks should be created for each profile, with up to four clocks per profile (TX, RX, CLKOUT1, and CLKOUT2). The netlist from the base profile should be used as the source for each clock. Additionally, you must specify physically exclusive clock groups across profile clocks in the constraints file.

For timing constraints, generate separate clocks for each profile and run the SDC analysis independently per profile. Identify the maximum frequency among all profiles and constrain the design accordingly. For example, based on the device, use a maximum frequency of 12 Gbps, applying the corresponding maximum CLKOUT frequency and minimum divisor value to the design. This approach is consistent with the method used in Ethernet for 10G.

The Multirate Ethernet PHY and SDI IPs utilize the GTS PMA/FEC Direct PHY IP for multirate support. However, not all IPs operate at the maximum frequency, as some work with lower line rates instead of the highest CLKOUT frequency.