GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

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ID 848344
Date 8/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS Transceiver Overview 2. GTS Transceiver Architecture 3. Implementing the GTS PMA/FEC Direct PHY IP 4. Implementing the GTS System PLL Clocks IP 5. Implementing the GTS Reset Sequencer IP 6. GTS PMA/FEC Direct PHY IP Example Design 7. Design Assistance Tools 8. Debugging GTS Transceiver Links with Transceiver Toolkit 9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs
1. GTS Transceiver Overview x
1.1. GTS Transceiver Design Flow
2. GTS Transceiver Architecture x
2.1. Building Blocks 2.2. Channel Placement Rules and Design Requirements 2.3. PMA Architecture 2.4. PCS Architecture 2.5. Forward Error Correction (FEC) Architecture 2.6. Clock Architecture 2.7. Bonding and Deskew
2.1. Building Blocks x
2.1.1. PMA 2.1.2. FEC 2.1.3. PCS 2.1.4. Ethernet MAC 2.1.5. PCI Express* Hard IP 2.1.6. PLL and Clock Networks 2.1.7. Avalon® Memory-Mapped Interface
2.1.1. PMA x
2.1.1.1. Protocol Support Using PMA Direct Mode
2.1.1.1. Protocol Support Using PMA Direct Mode x
2.1.1.1.1. SDI 2.1.1.1.2. HDMI 2.1.1.1.3. OTN
2.2. Channel Placement Rules and Design Requirements x
2.2.1. Hard IP Rules 2.2.2. Use Scenario Rules 2.2.3. Unused PMA Rules 2.2.4. General Design Requirement
2.2.3. Unused PMA Rules x
2.2.3.1. Unused PMA Not Planned for Use in the Future 2.2.3.2. Unused PMA Planned for Use in the Future
2.3. PMA Architecture x
2.3.1. Transmitter PMA Architecture 2.3.2. Receiver PMA Architecture 2.3.3. PMA Loopback Modes
2.3.1. Transmitter PMA Architecture x
2.3.1.1. Transmitter Buffer 2.3.1.2. Serializer 2.3.1.3. Data Pattern Generator and Verifier
2.3.2. Receiver PMA Architecture x
2.3.2.1. Receiver Buffer and Equalizer 2.3.2.2. Deserializer 2.3.2.3. CDR Block 2.3.2.4. RX PMA Tuning 2.3.2.5. RX PMA Adaptation Modes
2.3.2.1. Receiver Buffer and Equalizer x
2.3.2.1.1. Control Unit
2.3.2.5. RX PMA Adaptation Modes x
2.3.2.5.1. RX Auto Adaptation Mode 2.3.2.5.2. RX Manual Adaptation Mode 2.3.2.5.3. RX Native Adaptation Mode
2.5. Forward Error Correction (FEC) Architecture x
2.5.1. FEC Loopback Mode
2.6. Clock Architecture x
2.6.1. Reference Clock Network 2.6.2. Datapath Clock Network 2.6.3. System PLL 2.6.4. Datapath Clock Cadences 2.6.5. Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank
2.6.1. Reference Clock Network x
2.6.1.1. PMA Primary PLL Configuration
2.6.3. System PLL x
2.6.3.1. I/O PLL in HVIO Bank as System PLL 2.6.3.2. System PLL Clock for FPGA Core 2.6.3.3. System PLL with HVIO Reference Clock
2.7. Bonding and Deskew x
2.7.1. Bonding Architecture 2.7.2. TX Deskew Function
3. Implementing the GTS PMA/FEC Direct PHY IP x
3.1. IP Overview 3.2. Designing with the GTS PMA/FEC Direct PHY IP 3.3. Configuring the GTS PMA/FEC Direct PHY IP 3.4. Dynamically Reconfigurable PHY 3.5. Signal and Port Reference 3.6. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath 3.7. Clocking 3.8. Custom Cadence Generation Ports and Logic 3.9. Asserting Reset 3.10. Bonding Implementation 3.11. Configuration Register 3.12. Configuring the GTS PMA/FEC Direct PHY IP for Hardware Testing 3.13. Configurable Quartus® Prime Software Settings 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. PCS Direct Supported Modes 3.1.4. Unsupported PMA/FEC/PCS Modes
3.3. Configuring the GTS PMA/FEC Direct PHY IP x
3.3.1. Preset IP Parameter Settings 3.3.2. Mode and Common Datapath Options 3.3.3. TX Datapath Options 3.3.4. RX Datapath Options 3.3.5. PMA Configuration Rules for Specific Protocol Mode Implementations 3.3.6. FEC Options 3.3.7. PCS Options 3.3.8. Avalon® Memory-Mapped Interface Options 3.3.9. Register Map IP-XACT Support 3.3.10. Analog Parameter Options
3.3.2. Mode and Common Datapath Options x
3.3.2.1. Reconfigurable PHY Settings
3.3.3. TX Datapath Options x
3.3.3.1. TX PMA Interface Parameters
3.3.4. RX Datapath Options x
3.3.4.1. RX PMA Interface Parameters
3.3.5. PMA Configuration Rules for Specific Protocol Mode Implementations x
3.3.5.1. PMA Configuration Rules for SDI Mode 3.3.5.2. PMA Configuration Rules for HDMI Mode 3.3.5.3. PMA Configuration Rules for OTN Mode
3.4. Dynamically Reconfigurable PHY x
3.4.1. Clock Generation and Constraints for Multiple Profiles Design
3.5. Signal and Port Reference x
3.5.1. TX and RX Parallel and Serial Interface Signals 3.5.2. TX and RX Reference Clock and Clock Output Interface Signals 3.5.3. Reset Signals 3.5.4. FEC Signals 3.5.5. Custom Cadence Control and Status Signals 3.5.6. RX PMA Status Signals 3.5.7. TX and RX PMA and Core Interface FIFO Signals 3.5.8. Avalon Memory-Mapped Interface Signals
3.7. Clocking x
3.7.1. Clock Ports 3.7.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.7.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.7.4. PMA Fractional Mode 3.7.5. Input Reference Clock Buffer Protection 3.7.6. Guidelines for Obtaining the Real-Time GTS TX PLL Lock Status
3.7.5. Input Reference Clock Buffer Protection x
3.7.5.1. Reference Clock Buffer Register Information 3.7.5.2. Re-enabling the Reference Clock Buffers
3.8. Custom Cadence Generation Ports and Logic x
3.8.1. Implementing PMA Direct Mode with TX Core FIFO in Elastic Configuration 3.8.2. Enabling the i_tx_cadence_slow_clk_locked Port
3.9. Asserting Reset x
3.9.1. Reset Signal Requirements 3.9.2. Power On Reset Requirements 3.9.3. Reset Signals—Block Level 3.9.4. Run-time Reset Sequence—TX 3.9.5. Run-time Reset Sequence—RX 3.9.6. Run-time Reset Sequence—TX + RX 3.9.7. RX Data Loss/CDR Lock Loss (Auto-Recovery) 3.9.8. TX PLL Lock Loss
3.10. Bonding Implementation x
3.10.1. Bonding Placement Requirements 3.10.2. Multilane RX Simplex Implementation
3.11. Configuration Register x
3.11.1. GTS PMA and FEC Direct PHY Soft CSR Register Map 3.11.2. GTS PMA Register Map 3.11.3. Accessing Configuration Registers
3.11.2. GTS PMA Register Map x
3.11.2.1. Logical Avalon® Memory-Mapped Port Indexing
3.11.3. Accessing Configuration Registers x
3.11.3.1. Accessing GTS PMA and FEC Direct PHY Soft CSR Registers 3.11.3.2. Accessing GTS PMA Registers
3.12. Configuring the GTS PMA/FEC Direct PHY IP for Hardware Testing x
3.12.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY IP 3.12.2. Using JTAG to Avalon Master Bridge IP
3.12.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY IP x
3.12.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.12.2. Using JTAG to Avalon Master Bridge IP x
3.12.2.1. RTL Connection Example for JTAG to Avalon Master Bridge IP
3.13. Configurable Quartus® Prime Software Settings x
3.13.1. Configuring the RX Adaptation Mode and PMA Manual Tuning
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.14.1. Direct Register Method 3.14.2. GTS Attribute Access Method
3.14.1. Direct Register Method x
3.14.1.1. Direct Register Method Examples
3.14.2. GTS Attribute Access Method x
3.14.2.1. GTS Attribute Access Method Example 1: Enable or Disable Internal Serial Loopback Mode (RX Auto Adaptation Mode) 3.14.2.2. GTS Attribute Access Method Example 2: Enable or Disable Internal Serial Loopback Mode (RX Manual Adaptation Mode) 3.14.2.3. GTS Attribute Access Method Example 3: Enable or Disable Polarity Inversion of the PMA 3.14.2.4. GTS Attribute Access Method Example 4: Enable PRBS Generator and Checker to Run BER Test
4. Implementing the GTS System PLL Clocks IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for GTS System PLL Clocks IP Usage 4.5. Guidelines to Indicate System PLL Reference Clock is Ready
4.5. Guidelines to Indicate System PLL Reference Clock is Ready x
4.5.1. Example Flow to Indicate System PLL Reference Clock is Ready
5. Implementing the GTS Reset Sequencer IP x
5.1. IP Requirements 5.2. IP Parameters 5.3. IP Port List 5.4. GTS Reset Sequencer IP General Interface 5.5. GTS Reset Sequencer IP Design Flow 5.6. GTS Reset Sequencer IP Use Cases 5.7. Connecting the Reference Clock Buffer Status to the GTS Reset Sequencer IP
5.6. GTS Reset Sequencer IP Use Cases x
5.6.1. Example Use Case 1 5.6.2. Example Use Case 2
6. GTS PMA/FEC Direct PHY IP Example Design x
6.1. Instantiating the GTS PMA/FEC Direct PHY IP 6.2. Generating the GTS PMA/FEC Direct PHY IP Example Design 6.3. GTS PMA/FEC Direct PHY IP Example Design Functional Description 6.4. Simulating the GTS PMA/FEC Direct PHY IP Example Design Testbench 6.5. Compiling the GTS PMA/FEC Direct PHY IP Example Design 6.6. GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design 6.7. Generating the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable Example Design 6.8. GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design Functional Description 6.9. Simulating the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design Testbench 6.10. Compiling the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design
6.2. Generating the GTS PMA/FEC Direct PHY IP Example Design x
6.2.1. Fast Simulation Support 6.2.2. GTS PMA/FEC Direct PHY IP Example Design Directory Structure
6.4. Simulating the GTS PMA/FEC Direct PHY IP Example Design Testbench x
6.4.1. Modifying the Example Design and Performing Simulation
6.7. Generating the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable Example Design x
6.7.1. Fast Simulation Support 6.7.2. GTS PMA/FEC Direct PHY IP Reconfigurable PHY Example Design Directory Structure
7. Design Assistance Tools x
7.1. Clocking and Datapath Tool 7.2. TX Equalizer Tool
8. Debugging GTS Transceiver Links with Transceiver Toolkit x
8.1. GTS Transceiver Toolkit Parameter Settings 8.2. GTS Transceiver Toolkit GUI 8.3. GTS Transceiver Debugging Flow Walkthrough
8.2. GTS Transceiver Toolkit GUI x
8.2.1. Collection View
8.3. GTS Transceiver Debugging Flow Walkthrough x
8.3.1. Modifying the Design to Enable GTS Transceiver Debug Toolkit 8.3.2. Programming the Design into an Altera FPGA 8.3.3. Loading the Design to the Transceiver Toolkit 8.3.4. Creating Transceiver Links 8.3.5. Running BER Tests 8.3.6. Running Eye Viewer Tests 8.3.7. Running Link Optimization Tests
1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY IP
4. Implementing the GTS System PLL Clocks IP
5. Implementing the GTS Reset Sequencer IP
6. GTS PMA/FEC Direct PHY IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs

3.6. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath

The tx_parallel_data bit and rx_parallel_data bit width depends on the PMA width and Number of PMA lanes IP parameters. Use the following equation to determine the total tx_parallel_data or rx_parallel_data bit width:

Total tx_parallel_data or rx_parallel_data Bit Width Equation:

tx/rx_parallel_data[(80*N)-1:0]

Where:

  • N = Number of PMA lanes value from 1 to 4 .

The tx/rx_parallel_data signals include the valid parallel data bits and other functionality bits, such as the data valid bit, the write enable for TX core interface FIFO in elastic mode bit, the RX deskew bit, and the alignment marker bits (for FEC mode). These signals travel to and from the FPGA fabric to the transceiver block, and are clocked by the same parallel clock. This parallel clock can be a PMA clock or System PLL clock.

Example 1: Total tx/rx_parallel_data Bit Width with 2 PMA Lanes (N=2) and 8-bit PMA Width (X=1)

tx_parallel_data [(80*2)-1:0] = tx_parallel_data [159:0]
rx_parallel_data [(80*2)-1:0] = rx_parallel_data [159:0]

Parallel Data Mapping information for TX and RX

Table 44.  Variable Definitions
Variable Values Description
N 1, 2, 4 Number of lanes
n 0 to N-1 N is the PMA index number
D D = PMA Width D is the data width value to calculate the total parallel data bits
Table 45.  PMA Direct Mode Parallel Data Calculations
PMA Configuration MSB LSB TX Parallel Data RX Parallel Data

PMA Width = 8, 10, 16, 20, 32

Single Width

 79 Write Enable for TX Core FIFO in Elastic Mode 21 Data valid for RX Core FIFO in Elastic Mode21
38 + (80*n) TX PMA Interface Data Valid
Note: You must connect this bit to o_tx_cadence if you are using PMA Direct mode with PMA clocking in elastic mode. Elastic mode is only applicable for single lane operation.
RX PMA Interface Data Valid
[D-1] + (80*n) 0 + (80*n) TX Data RX Data

PMA Width = 8, 10, 16, 20, 32

Double Width

 79 Write Enable for TX Core FIFO in Elastic Mode21
Note: You must connect this bit to o_tx_cadence if you are using PMA Direct mode with PMA clocking in elastic mode. Elastic mode is only applicable for single lane operation.
Data valid for RX Core FIFO in Elastic Mode21
(40+D-1) + (80*n) 40 + (80*n) TX Data (Upper Data Bits) RX Data (Upper Data Bits)
38 + (80*n) TX PMA Interface Data Valid
Note: PMA Direct with PMA clocking in elastic mode. Elastic mode is only applicable for single lane operation.
RX PMA Interface Data Valid
(D -1) + (80*n) 0 + (80*n) TX Data (Lower Data Bits) RX Data (Lower Data Bits)
Table 46.  FEC Direct Mode Parallel Data Calculations
MSB LSB TX Parallel Data RX Parallel Data
77 Alignment Marker -
72 40 TX Data (Upper Data Bits) RX Data (Upper Data Bits)
38 TX PMA Interface Data Valid Bit RX PMA Interface Data Valid Bit
37 Alignment Marker Alignment Marker
32 2 TX Data (Lower Data Bits) RX Data (Lower Data Bits)
1 0 Sync Head
Table 47.  Example of Bit Mapping of TX Parallel Data Bits for PMA Direct Mode with PMA Width = 32
N (Number of Lanes) 1 2 … 4 TX Parallel Data
Bits 79    
Write Enable for TX Core FIFO in Elastic Mode.
Note: Bit 79 is only available for PMA Direct with PMA Clocking in Elastic mode and single lane operation.
38 118 … 278 TX PMA Interface Data Valid
31:0 118:80 … 271:240 TX Data (Lower Data Bits)
71:40 151:120 … 311:280 TX Data (Upper Data Bits)
Table 48.  PCS Direct Mode — IEEE MII Interface Parallel Data Calculations
MSB LSB TX Parallel Data RX Parallel Data
74 i_tx_mii_c[7] o_rx_mii_c[7]
73 66 i_tx_mii_d[63:56] o_rx_mii_d[63:56]
65 i_tx_mii_c[6] o_rx_mii_c[6]
64 57 i_tx_mii_d[55:48] o_rx_mii_d[55:48]
56 i_tx_mii_c[5] o_rx_mii_c[5]
55 48 i_tx_mii_d[47:40] o_rx_mii_d[47:40]
47 i_tx_mii_c[4] o_rx_mii_c[4]
46 39 i_tx_mii_d[39:32] o_rx_mii_d[39:32]
38 i_tx_mii_valid o_rx_mii_valid
37 i_tx_mii_am (RSFEC)

Reserved (Firecode FEC)

 o_rx_mii_am (RSFEC)

Reserved (Firecode FEC)
35 i_tx_mii_c[3] o_rx_mii_c[3]
34 27 i_tx_mii_d[31:24] o_rx_mii_d[31:24]
26 i_tx_mii_c[2] o_rx_mii_c[2]
25 18 i_tx_mii_d[23:16] o_rx_mii_d[23:16]
17 i_tx_mii_c[1] o_rx_mii_c[1]
16 9 i_tx_mii_d[15:8] o_rx_mii_d[15:8]
8 i_tx_mii_c[0] o_rx_mii_c[0]
7 0 i_tx_mii_d[7:0] o_rx_mii_d[7:0]
Table 49.  TX and RX Parallel Data to IEEE MII Port Mapping Signals for PCS Direct Mode
     
i_tx_mii_d[63:0] Input Drive MII encoded control bytes on this input data bus. i_tx_mii_d[7:0] holds the first byte the IP core transmits
i_tx_mii_c[7:0] Input For each control byte driven into i_tx_mii_d bus, drive the corresponding bit high. For example, i_tx_mii_c[0] corresponds to i_tx_mii_d[7:0]. If the value of a bit is 1, the corresponding data byte is a control byte. Otherwise it is data.
i_tx_mii_valid Input Drive this signal high to qualify the data or control bytes on the i_tx_mii_d bus.
i_tx_mii_am Input Alignment marker insertion bit (applicable only for RS-FEC). Drive this signal to 0 if Firecode FEC or FEC is not enabled.
o_rx_mii_d[63:0] Output Receive Ethernet frames or MII control bytes, MII encoded, on this input data bus. o_rx_mii_d[7:0] holds the first byte received.
o_rx_mii_c[15:0] Output Sample this bus to determine if o_rx_mii_d[63:0] input bus is carrying control or data bytes. If the value of a bit is 1, the corresponding data byte is a control byte. If the value of a bit is 0, the corresponding data byte is data.
o_rx_mii_valid Output Sample this signal to qualify the RX MII data, RX MII control bits, and the RX valid alignment marker signals.
Table 50.  PCS Direct Mode — IEEE_FLEXE_66/PCS66 Parallel Data Calculations
MSB LSB TX Parallel Data RX Parallel Data
71 39 i_txd[65:33] o_rxd[65:33]
38 i_tx_valid o_rx_valid
37 i_tx_am (RSFEC)

Reserved (Firecode FEC)

 o_rx_am (RSFEC)

Reserved (Firecode FEC)
32 0 i_txd[32:0] o_rxd[32:0]
Table 51.  TX and RX Parallel Data to IEEE_FLEXE_66/PCS66 Mapping Signals for PCS Direct Mode
Signal Name Direction Description
i_txd[65:0] Input Drive this data bus with the 66-bit data blocks from the source. The two least significant bits are the header sync bits. In FlexE mode, the TX PCS scrambles the 66-bit data block and stripes the data blocks across the transceiver channels. In PCS66 mode, you must provide scrambled data.
i_tx_valid Input Drive this signal high to qualify the 66-bit data block on the i_txd input data bus.
i_tx_am Input Drive valid 66-bit data blocks when this signal has been asserted. Do not drive valid data blocks when this signal is deasserted.
o_rxd[65:0] Output Output data bus that receives Ethernet frames or MII control bytes, MII encoded. o_rxd[7:0] holds the first byte received.
o_rx_valid Output PCS66 data valid signal. The signal indicates valid data on PCS66 ports.
o_rx_am Output Alignment marker indicator (applicable for RS-FEC). This signal indicates the blocks currently on o_rxd have been identified as alignment markers.
21 Only available for PMA clocking and if TX/RX core FIFO is in elastic mode.
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