Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 4/01/2024
Public

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3.1.3.4. Synopsys* VCS* MX Simulation Steps

  1. Locate your top-level simulation model.
    1. You can locate it at <project directory>/<Platform Designer design name>/sim/.
    2. Use the name located from the previous step (step a) to replace the placeholder names TopLevel.v and TopLevel that are used in the following steps.
  2. Locate the Cadence® setup script.
    1. You can locate it at <project directory>/<Platform Designer design name>/sim/synopsys/vcsmx/.
    2. Locate vcsmx_setup.sh.
  3. For this example, the simulator is executed in the sim/synopsys directory where the vcsmx_setup.sh file is located. Change directory to the sim/synopsys/vcsmx directory:
    cd <project directory>/<Platform Designer design name>/ \
    sim/synopsys/vcsmx/
  4. Copy the vcsmx_setup.sh file to another file. For this exercise, it is called my_vcs_script.sh.
    cp vcsmx_setup.sh my_vcsmx_script.sh
  5. In your my_vcsmx_script.sh file, delete everything except the section between the lines from "TOP-LEVEL TEMPLATE - BEGIN" to "TOP-LEVEL TEMPLATE - END".
  6. In your my_vcsmx_script.sh file, add additional libraries and flags by adding the following lines at the top of the file:
    rm -rf csrc libraries simv simv.daidir transcript \ 
    ucli.key vc_hdrs.h (optional)
    MVCHOME=<ACDS directory>/ip/altera/mentor_vip_ae/common/
    export QUESTA_MVC_GCC_LIB=${MVCHOME}/questa_mvc_core/ \
    linux_x86_64_gcc-6.2.0_vcs
    export LD_LIBRARY_PATH=${VCS_HOME}/gnu/linux/gcc-6.2.0/lib64
    
  7. Uncomment the first set of lines that source vcsmx_setup.sh in the template and modify to the following:
    source vcsmx_setup.sh \
    SKIP_ELAB=1 \
    SKIP_SIM=1
    
  8. Uncomment and modify the vlogan line in the template:
    vlogan ../../TopLevel.v
  9. After vlogan, export the LDFLAGS environment variable and pre-assign the elab options:
    export LDFLAGS="-L ${QUESTA_MVC_GCC_LIB} -Wl,-rpath \
     ${QUESTA_MVC_GCC_LIB} -laxi4_IN_SystemVerilog_VCS_full_DVC "
    USER_DEFINED_ELAB_OPTIONS="\" \
    -full64 \
    -timescale=1ns/1ns \
    +vpi -debug_access+r+w+nomemcbk +vcs+lic+wait \""
    
  10. Uncomment the second set of lines that source vcsmx_setup.sh in the template and modify to the following:
    source vcsmx_setup.sh \
    SKIP_DEV_COM=1 \
    SKIP_COM=1 \
    USER_DEFINED_ELAB_OPTIONS="$USER_DEFINED_ELAB_OPTIONS" \
    USER_DEFINED_SIM_OPTIONS="'-l transcript'" \
    TOP_LEVEL_NAME="'TopLevel'"
    
  11. Save the my_vcsmx_script.sh file.
  12. Setup your developer environment with the proper resources. Refer to Synopsys* documentation for downloading, installing, and licensing.
  13. Run the simulation script:
    sh my_vcsmx_script.sh
  14. The simulation is running without any errors. Since no testbench is added, it only shows that all the HPS IP simulation files were successfully compiled and elaborated.