Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 4/01/2024
Public

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3.2.3. FPGA-to-HPS Bridge (F2H)

This example instantiates an HPS initiator along with an On-Chip Memory subordinate component in Platform Designer. The testbench uses the Mentor Graphics* AXI* 4 Initiator BFM to model the HPS AXI* Bridge communication with the FPGA core logic.

  • AXI* Initiator Mentor Graphics* AXI* 4 Initiator BFM
  • AXI* Subordinate—On-Chip Memory

Setup:

  1. Download the Example Design using this link: Hard Processor System Component Reference Manual: Agilex™ 5 SoCs - FPGA-to-HPS Design Example.
  2. Uncompress the Example Design, the top directory is “agilex5_hps_f2h_simulation/”.
  3. In the top directory, verify the following items:
Table 13.  Description of Design Example items

File or directory

Description

agilex5_hps_f2h_simulation.qsys The top-level Platform Designer system file, which instantiates the HPS simulation model, a clock source, and a reset source.
ip/agilex5_hps_f2h_simulation The On-Chip Memory files
master_test_program.sv The Master Test Program file which initiates the transactions from HPS to FPGA fabric.
agilex5_hps_f2h_simulation_tb.v The testbench top file which contains the Platform Designer system and the Master Test Program instantiated along with clock and reset BFMs.
agilex5_hps_f2h_simulation_tb/ The directory contains the generated simulation scripts.
run.do The QuestaSim* simulation script which uses the generated script from Platform Designer and run the simulation.
wave.do The waveform file
Simulation Mechanism:
  1. The Platform Designer system consists of a HPS simulation model, a Clock Bridge, a Reset Bridge, and an On-Chip Memory.
    Figure 52.  Platform Designer System View
  2. The test program sends commands from the HPS BFM model using the f2h AXI* Bridge interface to the On-Chip memory.
  3. The test program performs a directed test to initiate four writes followed by four reads, and then followed by two write data bursts and two read data bursts.
  4. Finally, the test program verifies that the data read from the AXI* Subordinate memory matches the data written.