Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 4/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.2.2.4. Lightweight HPS to FPGA Manager

The Lightweight HPS-to-FPGA interface, a low-bandwidth control interface, allows HPS managers to issue transactions to the FPGA fabric.

  • Enable/Data Width dropdown to configure this manager interface's data widths
    • Unused
    • 32-bit
  • Interface Address Width is configurable to 29 bits down to 20 bits.
When this bridge is enabled, the interfaces lwhps2fpga, lwhps2fpga_axi_clock, and lwhps2fpga_axi_reset are made available.
Note: h2f_reset signal must be connected to lwhps2fpga_axi_reset signal for proper bridge operation.