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2.1. Parameterizing the HPS Component
2.2. HPS-FPGA Interfaces
2.3. SDRAM
2.4. HPS Clocks, Reset, Power
2.5. I/O Delays
2.6. Pin Mux and Peripherals
2.7. Generating and Compiling the HPS Component
2.8. Using the Address Span Extender Component
2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2.1.1. Enable MPU Standby and Event Signals
2.2.1.2. Enable General Purpose Signals
2.2.1.3. Enable Debug APB* Interface
2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events
2.2.1.5. Enable SWJ-DP JTAG Interface
2.2.1.6. Enable FPGA Cross Trigger Interface
2.2.1.7. Enable AMBA* Trace Bus (ATB)
3.1. Simulation Flows
3.2. Running the Simulation of the Design Examples
3.3. Clock and Reset Interface
3.4. FPGA-to-HPS AXI* Subordinate Interface
3.5. FPGA-to-SDRAM AXI* Subordinate Interface
3.6. HPS-to-FPGA AXI* Initiator Interface
3.7. Lightweight HPS-to-FPGA AXI* Initiator Interface
3.8. Simulating the Agilex™ 5 HPS Component Revision History
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2.4.3.1. Power Configurations
Agilex™ 5 HPS has four cores, you can select the core to power on and select the core to boot.
Figure 20. Platform Designer Power Configurations Sub-window
- Select power on Arm* Cortex*-A55 cores 0 and 1 by turning on the A55 Core-0-1 Power On option.
- Select power on Arm* Cortex*-A76 cores 2 and 3 by turning on the A76 Core-2 Power On and A76 Core-3 Power On.
- CPU Application drop-down to configure application mode of CPU cores to, Typical, Dhrystone, Max Power, Theoretical Max Power, Cold Reset, and Idle.
- Boot Core Selection drop-down to configure Core0 or Core2 to boot first. Only powered on cores can be selected
- MPU L3 Cache Size drop-down to configure MPU L3 cache size to Disable, 1MB, and 2MB.