Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 4/01/2024
Public

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Document Table of Contents

1.5. Interconnect

The system interconnect supports the following features:

  • Configurable Arm* TrustZone* -compliant firewall and security support.
    • Targets are placed in a secure or non-secure zone.
      • Secure targets can only be accessed by secure transactions.
      • Non-secure targets can be accessed by any transaction.
    • Allows configuration of individual transactions as secure or non-secure at the initiating initiator.
    • All targets are secure at reset.
      • Target secure state can be changed in NOC Security Control Registers (SCR).
    • Some initiators are secure at reset.
      • Initiator Secure state is driven on a per-transaction basis or by system manager.
    • Security Control Registers (SCRs) are strictly secure-only.
  • Multi-tiered bus structure to separate high bandwidth initiators from lower bandwidth targets and control and status ports.
  • Quality of service (QoS) with three programmable levels of service on a per initiator basis.
  • On-chip debugging and tracing capabilities.

The system interconnect is based on the Arteris* FlexNoC network-on-chip (NoC) interconnect technology.