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2.1. Parameterizing the HPS Component
2.2. HPS-FPGA Interfaces
2.3. SDRAM
2.4. HPS Clocks, Reset, Power
2.5. I/O Delays
2.6. Pin Mux and Peripherals
2.7. Generating and Compiling the HPS Component
2.8. Using the Address Span Extender Component
2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2.1.1. Enable MPU Standby and Event Signals
2.2.1.2. Enable General Purpose Signals
2.2.1.3. Enable Debug APB* Interface
2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events
2.2.1.5. Enable SWJ-DP JTAG Interface
2.2.1.6. Enable FPGA Cross Trigger Interface
2.2.1.7. Enable AMBA* Trace Bus (ATB)
3.1. Simulation Flows
3.2. Running the Simulation of the Design Examples
3.3. Clock and Reset Interface
3.4. FPGA-to-HPS AXI* Subordinate Interface
3.5. FPGA-to-SDRAM AXI* Subordinate Interface
3.6. HPS-to-FPGA AXI* Initiator Interface
3.7. Lightweight HPS-to-FPGA AXI* Initiator Interface
3.8. Simulating the Agilex™ 5 HPS Component Revision History
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1.5. Interconnect
The system interconnect supports the following features:
- Configurable Arm* TrustZone* -compliant firewall and security support.
- Targets are placed in a secure or non-secure zone.
- Secure targets can only be accessed by secure transactions.
- Non-secure targets can be accessed by any transaction.
- Allows configuration of individual transactions as secure or non-secure at the initiating initiator.
- All targets are secure at reset.
- Target secure state can be changed in NOC Security Control Registers (SCR).
- Some initiators are secure at reset.
- Initiator Secure state is driven on a per-transaction basis or by system manager.
- Security Control Registers (SCRs) are strictly secure-only.
- Targets are placed in a secure or non-secure zone.
- Multi-tiered bus structure to separate high bandwidth initiators from lower bandwidth targets and control and status ports.
- Quality of service (QoS) with three programmable levels of service on a per initiator basis.
- On-chip debugging and tracing capabilities.
The system interconnect is based on the Arteris* FlexNoC network-on-chip (NoC) interconnect technology.