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2.1. Parameterizing the HPS Component
2.2. HPS-FPGA Interfaces
2.3. SDRAM
2.4. HPS Clocks, Reset, Power
2.5. I/O Delays
2.6. Pin Mux and Peripherals
2.7. Generating and Compiling the HPS Component
2.8. Using the Address Span Extender Component
2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2.1.1. Enable MPU Standby and Event Signals
2.2.1.2. Enable General Purpose Signals
2.2.1.3. Enable Debug APB* Interface
2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events
2.2.1.5. Enable SWJ-DP JTAG Interface
2.2.1.6. Enable FPGA Cross Trigger Interface
2.2.1.7. Enable AMBA* Trace Bus (ATB)
3.1. Simulation Flows
3.2. Running the Simulation of the Design Examples
3.3. Clock and Reset Interface
3.4. FPGA-to-HPS AXI* Subordinate Interface
3.5. FPGA-to-SDRAM AXI* Subordinate Interface
3.6. HPS-to-FPGA AXI* Initiator Interface
3.7. Lightweight HPS-to-FPGA AXI* Initiator Interface
3.8. Simulating the Agilex™ 5 HPS Component Revision History
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2.6.2. EMAC PTP Interface
In the EMAC PTP interface section, there are options to turn on for each EMAC to enable the Precision Time Protocol (PTP) FPGA interface. These options are only applicable when an EMAC is routed to the HPS pins. When an EMAC is routed to the FPGA pins, these signals are automatically included in the emac<n> conduit. When enabled, the following signals are made available:
- emac<n>_ptp_pps_o,
- emac<n>_ptp_aux_tx_trig_i,
- emac<n>_ptp_tstmp_data,
- emac<n>_ptp_tstmp_en,
- emac_ptp_ref_clock clock input interface
Figure 28. Platform Designer EMAC PTP Interface Sub-window