Visible to Intel only — GUID: rif1686332937659
Ixiasoft
2.1. Parameterizing the HPS Component
2.2. HPS-FPGA Interfaces
2.3. SDRAM
2.4. HPS Clocks, Reset, Power
2.5. I/O Delays
2.6. Pin Mux and Peripherals
2.7. Generating and Compiling the HPS Component
2.8. Using the Address Span Extender Component
2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2.1.1. Enable MPU Standby and Event Signals
2.2.1.2. Enable General Purpose Signals
2.2.1.3. Enable Debug APB* Interface
2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events
2.2.1.5. Enable SWJ-DP JTAG Interface
2.2.1.6. Enable FPGA Cross Trigger Interface
2.2.1.7. Enable AMBA* Trace Bus (ATB)
3.1. Simulation Flows
3.2. Running the Simulation of the Design Examples
3.3. Clock and Reset Interface
3.4. FPGA-to-HPS AXI* Subordinate Interface
3.5. FPGA-to-SDRAM AXI* Subordinate Interface
3.6. HPS-to-FPGA AXI* Initiator Interface
3.7. Lightweight HPS-to-FPGA AXI* Initiator Interface
3.8. Simulating the Agilex™ 5 HPS Component Revision History
Visible to Intel only — GUID: rif1686332937659
Ixiasoft
2.4.2.5. Peripheral Clocks
This section contains options for setting the time-sensitive networking (TSN) clocks, precision time protocol (PTP) clocks, and other peripheral clocks such as GPIO debounce, PSI, and USB.
EMAC Channel Clocks only support two different frequencies and are appropriately gated between two counters generating 50 MHz and 250 MHz. The EMAC PTP has its own counter to provide a 100 MHz clock.
Figure 17. Platform Designer Peripheral Clocks Sub-window