Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 12/04/2023
Document Table of Contents

8.5. Placing LVDS Transmitters and Receivers in the Same GPIO-B Sub-Bank

If you want to place both LVDS transmitter and receiver interfaces in the same GPIO-B sub-bank, use an external PLL.
  • To use an external PLL, in the LVDS SERDES IP parameter editor, turn on the Use external PLL option.
  • You can generate two instances of the LVDS SERDES IP—a receiver and a transmitter.
  • In each instance, you can use up to the following number of channels:
    • 23 transmitters, with one inclock for the I/O PLL
    • 23 DPA or non-DPA receivers, with one inclock for the I/O PLL
    • 8 soft-CDR receivers
  • Generate the IOPLL Intel® FPGA IP and ensure that the .qsf file lists the IOPLL IP before the LVDS SERDES IP. This order is required for your design to compile with the proper clock constraints.
  • Connect the same PLL to both the transmitter and receiver instances. You can either use the coreclock from the LVDS transmitter instance or the coreclock from the LVDS receiver instance to clock your core logic. For the RX Soft-CDR mode, connect the coreclock of the LVDS transmitter instance to the ext_pll_1_outclock2 port of the LVDS receiver instance.
  • Set the I/O standard for the refclk port of the IOPLL IP to be compatible with the I/O standard used by the LVDS SERDES IP.
  • If you are using an external PLL, ensure that the PLL outclock frequency is the same as the LVDS data rate.
  • For DPA receiver LVDS interface that uses more than 4 bytes, use two external PLLs.